[PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2

Fri Aug 16 12:44:26 UTC 2024

Hi Ankit,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip drm-xe/drm-xe-next linus/master v6.11-rc3 next-20240816]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-i915-display-Add-support-for-SNPS-PHY-HDMI-PLL-algorithm-for-DG2/20240814-222404
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20240813031941.3553574-2-ankit.k.nautiyal%40intel.com
patch subject: [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2
config: i386-randconfig-061-20240816 (https://download.01.org/0day-ci/archive/20240816/202408162056.qbWTZcLT-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240816/202408162056.qbWTZcLT-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408162056.qbWTZcLT-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
   drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/slab.h, ...):
   include/linux/page-flags.h:235:46: sparse: sparse: self-comparison always evaluates to false
   include/linux/page-flags.h:235:46: sparse: sparse: self-comparison always evaluates to false
>> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c:103:23: sparse: sparse: cast truncates bits from constant value (e8d4a51000 becomes d4a51000)

vim +103 drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c

    47	
    48	static void get_ana_cp_int_prop(u32 vco_clk,
    49					u32 refclk_postscalar,
    50					int mpll_ana_v2i,
    51					int c, int a,
    52					const u64 curve_freq_hz[2][8],
    53					const u64 curve_0[2][8],
    54					const u64 curve_1[2][8],
    55					const u64 curve_2[2][8],
    56					u32 *ana_cp_int,
    57					u32 *ana_cp_prop)
    58	{
    59		u64 vco_div_refclk_float;
    60		u64 curve_0_interpolated;
    61		u64 curve_2_interpolated;
    62		u64 curve_1_interpolated;
    63		u64 curve_2_scaled1;
    64		u64 curve_2_scaled2;
    65		u64 adjusted_vco_clk1;
    66		u64 adjusted_vco_clk2;
    67		u64 curve_2_scaled_int;
    68		u64 interpolated_product;
    69		u64 scaled_interpolated_sqrt;
    70		u64 scaled_vco_div_refclk1;
    71		u64 scaled_vco_div_refclk2;
    72		u64 temp;
    73	
    74		vco_div_refclk_float = vco_clk * DIV_ROUND_DOWN_ULL(1000000000000ULL, refclk_postscalar);
    75	
    76		/* Interpolate curve values at the target vco_clk frequency */
    77		curve_0_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1],
    78					      curve_0[c][a], curve_0[c][a + 1]);
    79	
    80		curve_2_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1],
    81					      curve_2[c][a], curve_2[c][a + 1]);
    82	
    83		curve_1_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1],
    84					      curve_1[c][a], curve_1[c][a + 1]);
    85	
    86		curve_1_interpolated = DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE1_MULTIPLIER);
    87	
    88		/*
    89		 * Scale curve_2_interpolated based on mpll_ana_v2i, for integer part
    90		 * ana_cp_int and for the proportional part ana_cp_prop
    91		 */
    92		temp = curve_2_interpolated * (4 - mpll_ana_v2i);
    93		curve_2_scaled1 = DIV_ROUND_DOWN_ULL(temp, 16000);
    94		curve_2_scaled2 = DIV_ROUND_DOWN_ULL(temp, 160);
    95	
    96		/* Scale vco_div_refclk for ana_cp_int */
    97		scaled_vco_div_refclk1 = 112008301 * DIV_ROUND_DOWN_ULL(vco_div_refclk_float, 100000);
    98	
    99		adjusted_vco_clk1 = CURVE2_MULTIPLIER *
   100				    DIV_ROUND_DOWN_ULL(scaled_vco_div_refclk1, (curve_0_interpolated *
   101				    DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER)));
   102	
 > 103		*ana_cp_int = DIV_ROUND_CLOSEST_ULL(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1),
   104						    CURVE2_MULTIPLIER);
   105		*ana_cp_int = max(1, min(*ana_cp_int, 127));
   106	
   107		curve_2_scaled_int = curve_2_scaled1 * (*ana_cp_int);
   108	
   109		interpolated_product = curve_1_interpolated *
   110				       (curve_2_scaled_int * DIV_ROUND_DOWN_ULL(curve_0_interpolated,
   111									      CURVE0_MULTIPLIER));
   112	
   113		scaled_interpolated_sqrt =
   114				int_sqrt(DIV_ROUND_UP_ULL(interpolated_product, vco_div_refclk_float) *
   115				DIV_ROUND_DOWN_ULL(1000000000000ULL, 55));
   116	
   117		/* Scale vco_div_refclk for ana_cp_int */
   118		scaled_vco_div_refclk2 = DIV_ROUND_UP_ULL(vco_div_refclk_float, 1000000);
   119		adjusted_vco_clk2 = 1460281 * DIV_ROUND_UP_ULL(scaled_interpolated_sqrt *
   120							       scaled_vco_div_refclk2,
   121							       curve_1_interpolated);
   122	
   123		*ana_cp_prop = DIV_ROUND_UP_ULL(adjusted_vco_clk2, curve_2_scaled2);
   124		*ana_cp_prop = max(1, min(*ana_cp_prop, 127));
   125	}
   126	

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