[PATCH 01/12] drm/i915/display: Move all DSS control registers to a new file
Jani Nikula
jani.nikula at linux.intel.com
Mon Aug 26 11:46:01 UTC 2024
On Mon, 26 Aug 2024, Ankit Nautiyal <ankit.k.nautiyal at intel.com> wrote:
> Move all registers and bits related to dss ctl to a new file. While at it,
> use REG_* macros for the fields.
This actually makes review harder. Having separate commits for moving
stuff around and modification is *much* easier.
As a reviewer, if you apply the patches, it's really powerful to be able
to just look at 'git show --color-moved' on the movement patch, and 'git
show --color-words' on the modifications.
See for example:
git show 8c8667682e8414fd766c376219487a085f03e823 --color-moved
git show a9d32a4613082db444de623a513cb04809160e30 --color-words
BR,
Jani.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dss_regs.h | 49 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
> .../gpu/drm/i915/display/intel_vdsc_regs.h | 38 --------------
> 6 files changed, 53 insertions(+), 41 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dss_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 293efc1f841d..5ad5011e1fee 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -44,9 +44,9 @@
> #include "intel_de.h"
> #include "intel_dsi.h"
> #include "intel_dsi_vbt.h"
> +#include "intel_dss_regs.h"
> #include "intel_panel.h"
> #include "intel_vdsc.h"
> -#include "intel_vdsc_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 25ff3ff0ab95..4566a60c981c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -57,6 +57,7 @@
> #include "intel_dp_tunnel.h"
> #include "intel_dpio_phy.h"
> #include "intel_dsi.h"
> +#include "intel_dss_regs.h"
> #include "intel_encoder.h"
> #include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> @@ -74,7 +75,6 @@
> #include "intel_snps_phy.h"
> #include "intel_tc.h"
> #include "intel_vdsc.h"
> -#include "intel_vdsc_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1042f65967ba..8bce46bb7f3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -87,6 +87,7 @@
> #include "intel_drrs.h"
> #include "intel_dsb.h"
> #include "intel_dsi.h"
> +#include "intel_dss_regs.h"
> #include "intel_dvo.h"
> #include "intel_fb.h"
> #include "intel_fbc.h"
> @@ -118,7 +119,6 @@
> #include "intel_tv.h"
> #include "intel_vblank.h"
> #include "intel_vdsc.h"
> -#include "intel_vdsc_regs.h"
> #include "intel_vga.h"
> #include "intel_vrr.h"
> #include "intel_wm.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h
> new file mode 100644
> index 000000000000..462cc9aff4d7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DSS_REGS_H__
> +#define __INTEL_DSS_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* Display Stream Splitter Control */
> +#define DSS_CTL1 _MMIO(0x67400)
> +#define SPLITTER_ENABLE REG_BIT(31)
> +#define JOINER_ENABLE REG_BIT(30)
> +#define DUAL_LINK_MODE_INTERLEAVE REG_BIT(24)
> +#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> +#define OVERLAP_PIXELS_MASK REG_GENMASK(19, 16)
> +#define OVERLAP_PIXELS(pixels) REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels)
> +#define LEFT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(12, 0)
> +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, pixels)
> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
> +
> +#define DSS_CTL2 _MMIO(0x67404)
> +#define LEFT_BRANCH_VDSC_ENABLE REG_BIT(31)
> +#define RIGHT_BRANCH_VDSC_ENABLE REG_BIT(15)
> +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(12, 0)
> +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK, pixels)
> +
> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL1_PB, \
> + _ICL_PIPE_DSS_CTL1_PC)
> +#define BIG_JOINER_ENABLE REG_BIT(29)
> +#define PRIMARY_BIG_JOINER_ENABLE REG_BIT(28)
> +#define VGA_CENTERING_ENABLE REG_BIT(27)
> +#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> +#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> +#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> +#define UNCOMPRESSED_JOINER_PRIMARY REG_BIT(21)
> +#define UNCOMPRESSED_JOINER_SECONDARY REG_BIT(20)
> +
> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL2_PB, \
> + _ICL_PIPE_DSS_CTL2_PC)
> +
> +#endif /* __INTEL_DSS_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 2e849b015e74..891346f1f09a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -15,6 +15,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dsi.h"
> +#include "intel_dss_regs.h"
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
> #include "intel_vdsc_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index f921ad67b587..27c696e266af 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -8,44 +8,6 @@
>
> #include "intel_display_reg_defs.h"
>
> -/* Display Stream Splitter Control */
> -#define DSS_CTL1 _MMIO(0x67400)
> -#define SPLITTER_ENABLE (1 << 31)
> -#define JOINER_ENABLE (1 << 30)
> -#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
> -#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> -#define OVERLAP_PIXELS_MASK (0xf << 16)
> -#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> -#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> -#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
> -
> -#define DSS_CTL2 _MMIO(0x67404)
> -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
> -#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> -#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -
> -#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> -#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> -#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_PIPE_DSS_CTL1_PB, \
> - _ICL_PIPE_DSS_CTL1_PC)
> -#define BIG_JOINER_ENABLE (1 << 29)
> -#define PRIMARY_BIG_JOINER_ENABLE (1 << 28)
> -#define VGA_CENTERING_ENABLE (1 << 27)
> -#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> -#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> -#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> -#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21)
> -#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20)
> -
> -#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> -#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> -#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_PIPE_DSS_CTL2_PB, \
> - _ICL_PIPE_DSS_CTL2_PC)
> -
> /* Icelake Display Stream Compression Registers */
> #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
> #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
--
Jani Nikula, Intel
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