[PATCHv3 08/10] drm/i915/histogram: histogram delay counter doesnt reset

[Kandpal, Suraj]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces at lists.freedesktop.org> On Behalf Of
> Arun R Murthy
> Sent: Tuesday, December 3, 2024 11:25 AM
> To: intel-xe at lists.freedesktop.org; intel-gfx at lists.freedesktop.org; dri-
> devel at lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy at intel.com>
> Subject: [PATCHv3 08/10] drm/i915/histogram: histogram delay counter
> doesnt reset
> 
> The delay counter for histogram does not reset and as a result the histogram
> bin never gets updated. Workaround would be to use save and restore
> histogram register.
> 
> v2: Follow the seq in interrupt handler
> 	Restore DPST bit 0
> 	read/write dpst ctl rg
> 	Restore DPST bit 1 and Guardband Delay Interrupt counter = 0
> 	(Suraj)
> v3: updated wa version for display 13 and 14
> 
> Wa: 14014889975

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>

> Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_histogram.c     | 14 ++++++++++++++
>  .../gpu/drm/i915/display/intel_histogram_regs.h    |  2 ++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> b/drivers/gpu/drm/i915/display/intel_histogram.c
> index 8f25cfe00ba5..66006b75efaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> @@ -59,6 +59,11 @@ static void intel_histogram_handle_int_work(struct
> work_struct *work)
>  	snprintf(pipe_id, sizeof(pipe_id),
>  		 "PIPE=%u", intel_crtc->base.base.id);
> 
> +	/* Wa: 14014889975 */
> +	if (IS_DISPLAY_VER(display, 13, 14))
> +		intel_de_rmw(display, DPST_CTL(intel_crtc->pipe),
> +			     DPST_CTL_RESTORE, 0);
> +
>  	/*
>  	 * TODO: PSR to be exited while reading the Histogram data
>  	 * Set DPST_CTL Bin Reg function select to TC @@ -101,6 +106,15 @@
> static void intel_histogram_handle_int_work(struct work_struct *work)
>  		return;
>  	}
> 
> +	/* Wa: 14014889975 */
> +	if (IS_DISPLAY_VER(display, 13, 14))
> +		/* Write the value read from DPST_CTL to DPST_CTL.Interrupt
> Delay Counter(bit 23:16) */
> +		intel_de_rmw(display, DPST_CTL(intel_crtc->pipe),
> +			     DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT |
> +			     DPST_CTL_RESTORE,
> +			     DPST_CTL_GUARDBAND_INTERRUPT_DELAY(0x0) |
> +			     DPST_CTL_RESTORE);
> +
>  	/* Enable histogram interrupt */
>  	intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe),
> DPST_GUARD_HIST_INT_EN,
>  		     DPST_GUARD_HIST_INT_EN);
> diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> b/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> index 1252b4f339a6..213c9f483567 100644
> --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h
> @@ -16,6 +16,8 @@
>  #define  DPST_CTL_RESTORE				REG_BIT(28)
>  #define  DPST_CTL_IE_MODI_TABLE_EN			REG_BIT(27)
>  #define  DPST_CTL_HIST_MODE				REG_BIT(24)
> +#define  DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT
> 	REG_GENMASK(23, 16)
> +#define  DPST_CTL_GUARDBAND_INTERRUPT_DELAY(val)
> 	REG_FIELD_PREP(DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT,
> val)
>  #define  DPST_CTL_ENHANCEMENT_MODE_MASK
> 	REG_GENMASK(14, 13)
>  #define  DPST_CTL_EN_MULTIPLICATIVE
> 	REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2)
>  #define  DPST_CTL_IE_TABLE_VALUE_FORMAT			REG_BIT(15)
> --
> 2.25.1