[PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Arun R
> Murthy
> Sent: Monday, November 11, 2024 2:56 PM
> To: intel-xe at lists.freedesktop.org; intel-gfx at lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy at intel.com>
> Subject: [PATCHv4] drm/i915/dp: Guarantee a minimum HBlank time
> 
> Mandate a minimum Hblank symbol cycle count between BS and BE in
> 8b/10b MST and 12b/132b mode.

Missed the typo here *128

> Spec: DP2.1a
> 
> v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
> v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani)
> v4: use max/min functions, change intel_xx *intel_xx to intel_xx *xx
>     (Jani)
>     Limit hblank to 511 and accomodate BS/BE in calculated value
>     (Srikanth)
> 
> Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  1 +
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 35 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               |  4 +++
>  4 files changed, 41 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 705ec5ad385c..f8c1d1dd66a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -258,6 +258,7 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
>  			   str_enabled_disabled(pipe_config-
> >has_sel_update),
>  			   str_enabled_disabled(pipe_config-
> >has_panel_replay),
>  			   str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> +		drm_printf(&p, "minimum HBlank: %d\n", pipe_config-
> >min_hblank);
>  	}

Covers the dump but still missing the checker 
Also maybe a different patch for this work

> 
>  	drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", diff --
> git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d3a1aa7c919f..d2716addf88e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1075,6 +1075,7 @@ struct intel_crtc_state {
> 
>  	int max_link_bpp_x16;	/* in 1/16 bpp units */
>  	int pipe_bpp;		/* in 1 bpp units */
> +	int min_hblank;		/* min HBlank for DP2.1 */

Is it only for DP2.1 because we end up filling in both cases if uhbr or not just with different values

>  	struct intel_link_m_n dp_m_n;
> 
>  	/* m2_n2 for eDP downclock */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 13449c85162d..1e7482efe95c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -161,6 +161,35 @@ static int intel_dp_mst_dsc_get_slice_count(const
> struct intel_connector *connec
>  					    num_joined_pipes);
>  }
> 
> +static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state
> *crtc_state,
> +					    struct intel_connector *connector,
> +					    int bpp_x16)
> +{
> +	struct intel_encoder *encoder = connector->encoder;
> +	struct intel_display *display = to_intel_display(encoder);
> +	const struct drm_display_mode *adjusted_mode =
> +					&crtc_state->hw.adjusted_mode;
> +	int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> +	int hblank;
> +
> +	if (DISPLAY_VER(display) < 20)
> +		return;
> +
> +	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b
> MST & 128b/132b */
> +	hblank = DIV_ROUND_UP((DIV_ROUND_UP(adjusted_mode->htotal -
> +adjusted_mode->hdisplay, 4) * bpp_x16), symbol_size);
> +
> +	/* bit 8:0 minimum hblank symbol cylce count, i.e maximul value
 
Typo : Maximum

> would be 511 */
> +	hblank = min(511, hblank);
> +
> +	/* Software needs to adjust the BS/BE framing control from the
> valculated value */

Typo: Calculated

> +	hblank = hblank - 2;
> +
> +	if (intel_dp_is_uhbr(crtc_state))
> +		crtc_state->min_hblank = max(hblank, 5);
> +	else
> +		crtc_state->min_hblank = max(hblank, 3); }
> +
>  static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder
> *encoder,
>  						struct intel_crtc_state
> *crtc_state,
>  						int max_bpp,
> @@ -238,6 +267,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
>  		remote_bw_overhead =
> intel_dp_mst_bw_overhead(crtc_state, connector,
>  							      true,
> dsc_slice_count, link_bpp_x16);
> 
> +		intel_dp_mst_compute_min_hblank(crtc_state, connector,
> link_bpp_x16);
> +
>  		intel_dp_mst_compute_m_n(crtc_state, connector,
>  					 local_bw_overhead,
>  					 link_bpp_x16,
> @@ -1295,6 +1326,10 @@ static void intel_mst_enable_dp(struct
> intel_atomic_state *state,
>  			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz &
> 0xffffff));
>  	}
> 
> +	if (DISPLAY_VER(display) >= 20)
> +		intel_de_write(display, DP_MIN_HBLANK_CTL(trans),
> +			       pipe_config->min_hblank);
> +
>  	enable_bs_jitter_was(pipe_config);
> 
>  	intel_ddi_enable_transcoder_func(encoder, pipe_config); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> c160e087972a..0bd123276b9e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3485,6 +3485,10 @@
>  #define _TRANS_DP2_VFREQLOW_D			0x630a8
>  #define TRANS_DP2_VFREQLOW(trans)		_MMIO_TRANS(trans,
> _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
> 
> +#define _DP_MIN_HBLANK_CTL_A			0x600ac
> +#define _DP_MIN_HBLANK_CTL_B			0x610ac
> +#define DP_MIN_HBLANK_CTL(trans)		_MMIO_TRANS(trans,
> _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
> +
>  /* SNB eDP training params */
>  /* SNB A-stepping */
>  #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
> --
> 2.25.1