[PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

Hogander, Jouni jouni.hogander at intel.com
Mon May 6 07:34:55 UTC 2024


On Thu, 2024-05-02 at 13:40 +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> > On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
> > > Avoid the implicit dev_priv local variable use, and pass dev_priv
> > > explicitly to the ALPM_CTL2 register macro.
> > > 
> > > Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > index 4d950b22d4f1..05dc1c1d4ac2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > @@ -321,7 +321,7 @@
> > >  #define 
> > > ALPM_CTL_AUX_LESS_WAKE_TIME(val)              REG_FIELD_PREP(ALPM
> > > _CTL_AUX_LESS_WAKE_TIME_MASK, val)
> > >  
> > >  #define _ALPM_CTL2_A   0x60954
> > > -#define ALPM_CTL2(tran)        _MMIO_TRANS2(dev_priv, tran,
> > > _ALPM_CTL2_A)
> > > +#define ALPM_CTL2(dev_priv, tran)      _MMIO_TRANS2(dev_priv,
> > > tran, _ALPM_CTL2_A)
> > 
> > no usage? should we just delete it?
> 
> I believe a recent addition to enable ALPM. Jouni?

I added it together with other ALPM registers. Currently there is only
one field for LunarLake and we are not changing it from the default. I
would still keep it.

Reviewed-by: Jouni Högander <jouni.hogander at intel.com>


> 
> BR,
> Jani.
> 
> > 
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK               REG_GENMASK
> > > (28, 24)
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)               REG_FIELD_P
> > > REP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
> > >  #define 
> > > ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK           REG_GENMASK
> > > (19, 16)
> > > -- 
> > > 2.39.2
> > > 
> 



More information about the Intel-gfx mailing list