[PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers

[Imre Deak]

On Thu, Jan 02, 2025 at 11:39:07AM +0200, Jani Nikula wrote:
> On Tue, 31 Dec 2024, Imre Deak <imre.deak at intel.com> wrote:
> > On Thu, Dec 19, 2024 at 11:34:00PM +0200, Jani Nikula wrote:
> >> Write the DP2 specific VFREQ registers.
> >> 
> >> This is preparation for enabling 128b/132b SST. This path is not
> >> reachable yet.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++++++
> >>  1 file changed, 12 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index 64528ff8856e..91e6cd91e91f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -3467,8 +3467,20 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
> >>  {
> >>  	struct intel_display *display = to_intel_display(encoder);
> >>  	struct intel_crtc *pipe_crtc;
> >> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >>  	int i;
> >>  
> >> +	/* 128b/132b SST */
> >> +	if (intel_dp_is_uhbr(crtc_state)) {
> >
> > Hm, not sure how this would work on HDMI (FRL), but to be sure shouldn't
> > this check that crtc_state is for a DP (SST) mode?
> 
> DP MST does not call intel_ddi_enable().

I meant that this function (intel_ddi_enable()) can be called for HDMI
as well, in case of HDMI FRL with port clock being >= 10G. In that case
this - and the payload related bits later - shouldn't be programmed. So
would need if (!hdmi && intel_dp_is_uhbr()).

> Yes, it's all very subtle, and I hate the way all of the
> DDI/SST/MST/etc. is intertwined, but I feel like it's overall a bigger
> refactoring to clean up.
> 
> BR,
> Jani.
> 
> 
> >
> >> +		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> +		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
> >> +
> >> +		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
> >> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
> >> +		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
> >> +			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> >> +	}
> >> +
> >>  	intel_ddi_enable_transcoder_func(encoder, crtc_state);
> >>  
> >>  	/* Enable/Disable DP2.0 SDP split config before transcoder */
> >> -- 
> >> 2.39.5
> >> 
> 
> -- 
> Jani Nikula, Intel