[PATCH v4 06/11] mtd: intel-dg: align 64bit read and write

[David Laight]

On Wed, 1 Jan 2025 16:41:19 +0000
David Laight <david.laight.linux at gmail.com> wrote:

> On Wed,  1 Jan 2025 17:39:20 +0200
> Alexander Usyskin <alexander.usyskin at intel.com> wrote:
> 
> > GSC NVM controller HW errors on quad access overlapping 1K border.
> > Align 64bit read and write to avoid readq/writeq over 1K border.
> > 
> > Acked-by: Miquel Raynal <miquel.raynal at bootlin.com>
> > Signed-off-by: Alexander Usyskin <alexander.usyskin at intel.com>
> > ---
> >  drivers/mtd/devices/mtd-intel-dg.c | 35 ++++++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-intel-dg.c
> > index 76ef7198fff8..230bf444b7fe 100644
> > --- a/drivers/mtd/devices/mtd-intel-dg.c
> > +++ b/drivers/mtd/devices/mtd-intel-dg.c
> > @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
> >  		len_s -= to_shift;
> >  	}
> >  
> > +	if (!IS_ALIGNED(to, sizeof(u64)) &&
> > +	    ((to ^ (to + len_s)) & GENMASK(31, 10))) {  

That might as well be the easier to understand:
	if ((to & 7) && (to & 1023) + len_s > 1024)

Replacing (add, xor, and) with (and, add, cmp) is much the same
even without the decrement.

	David