[PATCH] drm/i915: Add Wa_22010465259 in its respective WA list

Bhadane, Dnyaneshwar dnyaneshwar.bhadane at intel.com
Thu Jan 16 05:24:07 UTC 2025



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ranu
> Maurya
> Sent: Wednesday, January 15, 2025 1:22 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Pottumuttu, Sai Teja <sai.teja.pottumuttu at intel.com>; Vivekanandan,
> Balasubramani <balasubramani.vivekanandan at intel.com>; Maurya, Ranu
> <ranu.maurya at intel.com>
> Subject: [PATCH] drm/i915: Add Wa_22010465259 in its respective WA list
> 
> Add Wa_22010465259 which points to an existing WA, but was missing from
> the comment list. While at it, update the other WAs and their applicable
> platforms as well.
> 
> Signed-off-by: Ranu Maurya <ranu.maurya at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 570c91878189..277a4df31071 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -691,16 +691,17 @@ static void gen12_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  	struct drm_i915_private *i915 = engine->i915;
> 
>  	/*
> -	 * Wa_1409142259:tgl,dg1,adl-p
> +	 * Wa_1409142259:tgl,dg1,adl-p,adl-n
>  	 * Wa_1409347922:tgl,dg1,adl-p
>  	 * Wa_1409252684:tgl,dg1,adl-p
>  	 * Wa_1409217633:tgl,dg1,adl-p
>  	 * Wa_1409207793:tgl,dg1,adl-p
> -	 * Wa_1409178076:tgl,dg1,adl-p
> -	 * Wa_1408979724:tgl,dg1,adl-p
> -	 * Wa_14010443199:tgl,rkl,dg1,adl-p
> -	 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
> -	 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
> +	 * Wa_1409178076:tgl,dg1,adl-p,adl-n
> +	 * Wa_1408979724:tgl,dg1,adl-p,adl-n
> +	 * Wa_14010443199:tgl,rkl,dg1,adl-p,adl-n
^^^ Please include DG2 in above platform list.

> +	 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p,adl-n
^^^ Add DG2 in above list. 

With these changes LGTM. 

Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com> 

Regards,
Dnyaneshwar
> +	 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p,adl-n
> +	 * Wa_22010465259:tgl,rkl,dg1,adl-s,adl-p,adl-n
>  	 */
>  	wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
>  		     GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> --
> 2.25.1



More information about the Intel-gfx mailing list