[PATCH 9/9] drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 11, 2025 9:23 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: intel-xe at lists.freedesktop.org
> Subject: [PATCH 9/9] drm/i915/dmc: Do not enable the pipe DMC on TGL when
> PSR is possible
> 
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> On TGL/derivatives the pipe DMC state is lost when PG1 is disabled, and the
> main DMC does not restore any of it. This means the state will also be lost during
> PSR+DC5/6. It seems safest to not even enable the pipe DMC in that case (the
> main DMC does restore the pipe DMC enable bit in PIPEDMC_CONTROL_A for
> some reason).
> 
> Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
> actually losing anything here. In the future if we do want to enable "fast LACE"
> we'll just have to remember that it won't be compatible with PSR.

Changes Look Good to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 0562ee1d0905..f918d08acd0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -663,6 +663,21 @@ static bool need_pipedmc_load_mmio(struct
> intel_display *display, enum pipe pipe
>  	return DISPLAY_VER(display) >= 30 && pipe >= PIPE_C;  }
> 
> +static bool can_enable_pipedmc(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	/*
> +	 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled.
> +	 * Do not even enable the pipe DMC when that can happen outside
> +	 * of driver control (PSR+DC5/6).
> +	 */
> +	if (DISPLAY_VER(display) == 12 && crtc_state->has_psr)
> +		return false;
> +
> +	return true;
> +}
> +
>  void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state); @@ -673,6
> +688,11 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state
> *crtc_state)
>  	if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
>  		return;
> 
> +	if (!can_enable_pipedmc(crtc_state)) {
> +		intel_dmc_disable_pipe(crtc_state);
> +		return;
> +	}
> +
>  	if (need_pipedmc_load_program(display))
>  		dmc_load_program(display, dmc_id);
>  	else if (need_pipedmc_load_mmio(display, pipe))
> --
> 2.49.0