[PATCH v3 3/4] drm/i915/gvt: Remove MMIO barrier in MMIO switch
changbin.du at intel.com
changbin.du at intel.com
Fri Dec 8 06:56:22 UTC 2017
From: Changbin Du <changbin.du at intel.com>
After engine mmio switched, software still need write workload
submission registers. So we can remove the MMIO barriar in MMIO
switch.
Signed-off-by: Changbin Du <changbin.du at intel.com>
---
drivers/gpu/drm/i915/gvt/render.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index 584f41a..8a52b56 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -275,7 +275,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
u32 inhibit_mask =
_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
- i915_reg_t last_reg = _MMIO(0);
struct engine_mmio *mmio;
u32 v;
@@ -304,17 +303,12 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
v = vgpu_vreg(vgpu, mmio->reg);
I915_WRITE_FW(mmio->reg, v);
- last_reg = mmio->reg;
trace_render_mmio(vgpu->id, "load",
i915_mmio_reg_offset(mmio->reg),
mmio->value, v);
}
- /* Make sure the swiched MMIOs has taken effect. */
- if (likely(i915_mmio_reg_offset(last_reg)))
- I915_READ_FW(last_reg);
-
handle_tlb_pending_event(vgpu, ring_id);
}
@@ -322,7 +316,6 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- i915_reg_t last_reg = _MMIO(0);
struct engine_mmio *mmio;
u32 v;
@@ -346,16 +339,11 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
continue;
I915_WRITE_FW(mmio->reg, v);
- last_reg = mmio->reg;
trace_render_mmio(vgpu->id, "restore",
i915_mmio_reg_offset(mmio->reg),
mmio->value, v);
}
-
- /* Make sure the swiched MMIOs has taken effect. */
- if (likely(i915_mmio_reg_offset(last_reg)))
- I915_READ_FW(last_reg);
}
/**
--
2.7.4
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