[PATCH v2] drm/i915/gvt: refine function emulate_mmio_read/write

Zhenyu Wang zhenyuw at linux.intel.com
Fri Dec 8 08:32:45 UTC 2017


On 2017.12.08 15:33:17 +0800, Pei Zhang wrote:
> These 2 functions are coded by multiple person in multiple patches. The
> 'return' and 'goto err' are mix-used in same place, which cause the
> function looks disorder. Unify to use only 'goto' so that the gvt lock
> is acquired in one place and released in one place.
> 
> Signed-off-by: Pei Zhang <pei.zhang at intel.com>
> ---

Looks can't apply cleanly onto current staging, could you rebase?


>  drivers/gpu/drm/i915/gvt/mmio.c | 32 ++++++++++++++------------------
>  1 file changed, 14 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
> index 980ec89..24f9c2f 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> @@ -126,13 +126,12 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
>  	unsigned int offset = 0;
>  	int ret = -EINVAL;
>  
> -
>  	if (vgpu->failsafe) {
>  		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
>  		return 0;
>  	}
> -	mutex_lock(&gvt->lock);
>  
> +	mutex_lock(&gvt->lock);
>  	if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
>  		struct intel_vgpu_guest_page *gp;
>  
> @@ -146,8 +145,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
>  					ret, gp->gfn, pa, *(u32 *)p_data,
>  					bytes);
>  			}
> -			mutex_unlock(&gvt->lock);
> -			return ret;
> +			goto out;
>  		}
>  	}
>  
> @@ -168,14 +166,12 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
>  				p_data, bytes);
>  		if (ret)
>  			goto err;
> -		mutex_unlock(&gvt->lock);
> -		return ret;
> +		goto out;
>  	}
>  
>  	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
>  		ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
> -		mutex_unlock(&gvt->lock);
> -		return ret;
> +		goto out;
>  	}
>  
>  	if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
> @@ -191,11 +187,13 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
>  		goto err;
>  
>  	intel_gvt_mmio_set_accessed(gvt, offset);
> -	mutex_unlock(&gvt->lock);
> -	return 0;
> +	ret = 0;
> +	goto out;
> +
>  err:
>  	gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
>  			offset, bytes);
> +out:
>  	mutex_unlock(&gvt->lock);
>  	return ret;
>  }
> @@ -237,8 +235,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
>  					ret, gp->gfn, pa,
>  					*(u32 *)p_data, bytes);
>  			}
> -			mutex_unlock(&gvt->lock);
> -			return ret;
> +			goto out;
>  		}
>  	}
>  
> @@ -259,14 +256,12 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
>  				p_data, bytes);
>  		if (ret)
>  			goto err;
> -		mutex_unlock(&gvt->lock);
> -		return ret;
> +		goto out;
>  	}
>  
>  	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
>  		ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
> -		mutex_unlock(&gvt->lock);
> -		return ret;
> +		goto out;
>  	}
>  
>  	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
> @@ -274,11 +269,12 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
>  		goto err;
>  
>  	intel_gvt_mmio_set_accessed(gvt, offset);
> -	mutex_unlock(&gvt->lock);
> -	return 0;
> +	ret = 0;
> +	goto out;
>  err:
>  	gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
>  		     bytes);
> +out:
>  	mutex_unlock(&gvt->lock);
>  	return ret;
>  }
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 195 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/intel-gvt-dev/attachments/20171208/403b372e/attachment.sig>


More information about the intel-gvt-dev mailing list