[PATCH v2] drm/i915/gvt: Fix gen8/9_render_mmio_list[0] don't take effect

[Zhenyu Wang]

On 2017.12.26 08:48:39 +0800, Xiong Zhang wrote:
> while(mmio++) increase mmio to next, mmio[0] never take effect
> in while loop.
> 
> This patch change while to for and fix the above issue.
> 
> v2: Correct Fixes format.(Zhenyu)
> 
> Fixes: 83164886e455("drm/i915/gvt: Select appropriate mmio list
>                      at initialization time")

why wrap Fixes line? checkpatch warning? should keep on one single line.

Pls rebase against latest staging, failed to apply here. thanks

> Signed-off-by: Xiong Zhang <xiong.y.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/mmio_context.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 8a52b56..177ae6c 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -80,7 +80,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
>  	{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
>  	{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
>  	{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
> -	{ /* Terminated */ }
> +	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
>  };
>  
>  static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> @@ -146,7 +146,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
>  	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
>  	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
>  	{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
> -	{ /* Terminated */ }
> +	{RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
>  };
>  
>  static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
> @@ -281,8 +281,8 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		load_mocs(vgpu, ring_id);
>  
> -	mmio = vgpu->gvt->engine_mmio_list;
> -	while (i915_mmio_reg_offset((mmio++)->reg)) {
> +	for (mmio = vgpu->gvt->engine_mmio_list;
> +	     i915_mmio_reg_valid(mmio->reg); mmio++) {
>  		if (mmio->ring_id != ring_id)
>  			continue;
>  
> @@ -322,8 +322,8 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>  		restore_mocs(vgpu, ring_id);
>  
> -	mmio = vgpu->gvt->engine_mmio_list;
> -	while (i915_mmio_reg_offset((mmio++)->reg)) {
> +	for (mmio = vgpu->gvt->engine_mmio_list;
> +	     i915_mmio_reg_valid(mmio->reg); mmio++) {
>  		if (mmio->ring_id != ring_id)
>  			continue;
>  
> -- 
> 2.7.4
> 

-- 
Open Source Technology Center, Intel ltd.

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