[PATCH] drm/i915/gvt: add pcode read/write emulation of BDW

[Zhenyu Wang]

On 2017.02.24 06:26:27 +0000, Li, Weinan Z wrote:
> > @@ -2544,7 +2548,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> >  	MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
> >  	MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL,
> > skl_power_well_ctl_write);
> > 
> > -	MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write);
> It will call init_generic_mmio_info-> init_broadwell_mmio_info-> init_skl_mmio_info if it's skylake,
> that's why there is dup definition before, we also define it in init_broadwell_mmio_info

yeah, sure, we need one handler to cover different hw.

-- 
Open Source Technology Center, Intel ltd.

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