[PATCH] drm/i915/gvt: Add support for framebuffer decoding
Tian, Kevin
kevin.tian at intel.com
Fri Mar 24 02:31:51 UTC 2017
please use plain text format.
Also since there is no user of this API, I don't think we can accept it now.
From: intel-gvt-dev [mailto:intel-gvt-dev-bounces at lists.freedesktop.org] On Behalf Of Liu, Yang2
Sent: Friday, March 24, 2017 10:30 AM
To: intel-gvt-dev at lists.freedesktop.org
Cc: Liu, Yang2 <yang2.liu at intel.com>
Subject: [PATCH] drm/i915/gvt: Add support for framebuffer decoding
This patch decode the frambuffer attributes, and provide some API for usage like surface size calculation.
Signed-off-by: Yang Liu <yang2.liu at intel.com<mailto:yang2.liu at intel.com>>
---
drivers/gpu/drm/i915/gvt/Makefile | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 403 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/fb_decoder.h | 88 ++++++++
drivers/gpu/drm/i915/gvt/gvt.h | 1 +
drivers/gpu/drm/i915/gvt/reg.h | 40 ++++
5 files changed, 533 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h
diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
index b123c20..2243fce 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,7 @@
GVT_DIR := gvt
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
- execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+ execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+fb_decoder.o
ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
new file mode 100644
index 0000000..a09f17c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+"Software"),
+ * to deal in the Software without restriction, including without
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+next
+ * paragraph) shall be included in all copies or substantial portions
+of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Kevin Tian <kevin.tian at intel.com<mailto:kevin.tian at intel.com>>
+ *
+ * Contributors:
+ * Ping Gao <ping.a.gao at intel.com<mailto:ping.a.gao at intel.com>>
+ * Xiaoguang Chen <xiaoguang.chen at intel.com<mailto:xiaoguang.chen at intel.com>>
+ * Yang Liu <yang2.liu at intel.com<mailto:yang2.liu at intel.com>>
+ *
+ */
+
+#include "i915_drv.h"
+#include "gvt.h"
+#include <uapi/drm/drm_fourcc.h>
+
+/* The below definitions are required by guest. */ // [63:0] x:R:G:B
+16:16:16:16 little endian #define DRM_FORMAT_XRGB161616_GVT
+fourcc_code('X', 'R', '4', '8') // [63:0] x:B:G:R 16:16:16:16 little
+endian #define DRM_FORMAT_XBGR161616_GVT fourcc_code('X', 'B', '4',
+'8')
+
+static struct pixel_format preskl_pixel_formats[] = {
+ [0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+ [0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+ [0x6] = {DRM_FORMAT_XRGB8888, 32,
+ "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+ [0x8] = {DRM_FORMAT_XBGR2101010, 32,
+ "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
+ [0xa] = {DRM_FORMAT_XRGB2101010, 32,
+ "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+ [0xc] = {DRM_FORMAT_XRGB161616_GVT, 64,
+ "64-bit RGBX Floating Point(16:16:16:16 MSB-X:B:G:R)"},
+ [0xe] = {DRM_FORMAT_XBGR8888, 32,
+ "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, };
+
+static struct pixel_format skl_pixel_formats[] = {
+ {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
+ {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
+ {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
+ {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
+
+ {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+ {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+ {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
+ {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+
+ {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
+ {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
+ {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XRGB161616_GVT, 64,
+ "64-bit XRGB (16:16:16:16 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XBGR161616_GVT, 64,
+ "64-bit XBGR (16:16:16:16 MSB-X:B:G:R)"},
+
+ /* non-supported format has bpp default to 0 */
+ {0, 0, NULL},
+};
+
+static struct pixel_format preskl_pixel_formats_sprite[] = {
+ [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
+ [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
+ [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
+ [0x3] = {DRM_FORMAT_XRGB161616_GVT, 64,
+ "RGB 64-bit 16:16:16:16 Floating Point"},
+ [0x4] = {DRM_FORMAT_AYUV, 32,
+ "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, };
+
+
+static int gen8_get_pixel_format(u32 plane_ctl,
+ struct intel_vgpu_common_plane_format *com_plane_fmt,
+ enum intel_gvt_plane_type plane)
+{
+ u32 color_order, yuv_order;
+ int drm_format;
+
+ if (plane != PRIMARY_PLANE && plane != SPRITE_PLANE)
+ return -EINVAL;
+
+ if (plane == PRIMARY_PLANE) {
+ com_plane_fmt->tiled = !!(plane_ctl & DISPPLANE_TILED);
+ com_plane_fmt->fmt_index = (plane_ctl &
+ DISPPLANE_PIXFORMAT_MASK) >> _PRI_PLANE_FMT_SHIFT;
+
+ memcpy(&com_plane_fmt->gen_pixel_format,
+ &preskl_pixel_formats[com_plane_fmt->fmt_index],
+ sizeof(struct pixel_format));
+
+ com_plane_fmt->stride_mask = _PRI_PLANE_STRIDE_MASK;
+ } else {
+ com_plane_fmt->tiled = !!(plane_ctl & SPRITE_TILED);
+ com_plane_fmt->fmt_index = (plane_ctl & SPRITE_PIXFORMAT_MASK)
+ >> _SPRITE_FMT_SHIFT;
+ color_order = !!(plane_ctl & SPRITE_RGB_ORDER_RGBX);
+ yuv_order = (plane_ctl & SPRITE_YUV_BYTE_ORDER_MASK)
+ >> _SPRITE_YUV_ORDER_SHIFT;
+
+ memcpy(&com_plane_fmt->gen_pixel_format,
+ &preskl_pixel_formats_sprite[com_plane_fmt->fmt_index],
+ sizeof(struct pixel_format));
+
+ com_plane_fmt->stride_mask = _SPRITE_STRIDE_MASK;
+
+ drm_format = com_plane_fmt->gen_pixel_format.drm_format;
+
+ if (!color_order) {
+ if (drm_format == DRM_FORMAT_XRGB2101010)
+ drm_format = DRM_FORMAT_XBGR2101010;
+ else if (drm_format == DRM_FORMAT_XRGB8888)
+ drm_format = DRM_FORMAT_XBGR8888;
+ else if (drm_format == DRM_FORMAT_XRGB161616_GVT)
+ drm_format = DRM_FORMAT_XBGR161616_GVT;
+ }
+
+ if (drm_format == DRM_FORMAT_YUV422) {
+ switch (yuv_order) {
+ case 0:
+ drm_format = DRM_FORMAT_YUYV;
+ break;
+ case 1:
+ drm_format = DRM_FORMAT_UYVY;
+ break;
+ case 2:
+ drm_format = DRM_FORMAT_YVYU;
+ break;
+ case 3:
+ drm_format = DRM_FORMAT_VYUY;
+ break;
+ default:
+ /* yuv_order has only 2 bits */
+ return -EINVAL;
+ }
+ }
+
+ com_plane_fmt->gen_pixel_format.drm_format = drm_format;
+ }
+
+ return 0;
+}
+
+static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
+ int yuv_order)
+{
+ int skl_pixel_formats_index = 14;
+
+ switch (format) {
+ case PLANE_CTL_FORMAT_INDEXED:
+ skl_pixel_formats_index = 4;
+ break;
+
+ case PLANE_CTL_FORMAT_RGB_565:
+ skl_pixel_formats_index = 5;
+ break;
+
+ case PLANE_CTL_FORMAT_XRGB_8888:
+ if (rgb_order) {
+ if (alpha)
+ skl_pixel_formats_index = 6;
+ else
+ skl_pixel_formats_index = 7;
+ } else {
+ if (alpha)
+ skl_pixel_formats_index = 8;
+ else
+ skl_pixel_formats_index = 9;
+ }
+ break;
+
+ case PLANE_CTL_FORMAT_XRGB_2101010:
+ if (rgb_order)
+ skl_pixel_formats_index = 10;
+ else
+ skl_pixel_formats_index = 11;
+ break;
+
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ if (rgb_order)
+ skl_pixel_formats_index = 12;
+ else
+ skl_pixel_formats_index = 13;
+ break;
+
+ case PLANE_CTL_FORMAT_YUV422:
+ skl_pixel_formats_index = yuv_order >> 16;
+ if (skl_pixel_formats_index > 3)
+ return -EINVAL;
+ break;
+
+ default:
+ break;
+ }
+
+ return skl_pixel_formats_index;
+}
+
+static int skl_get_pixel_format(u32 plane_ctl,
+ struct intel_vgpu_common_plane_format *com_plane_fmt,
+ enum intel_gvt_plane_type plane)
+{
+ com_plane_fmt->tiled = plane_ctl & PLANE_CTL_TILED_MASK;
+ com_plane_fmt->fmt_index = skl_format_to_drm(
+ plane_ctl & PLANE_CTL_FORMAT_MASK,
+ plane_ctl & PLANE_CTL_ORDER_RGBX,
+ plane_ctl & PLANE_CTL_ALPHA_MASK,
+ plane_ctl & PLANE_CTL_YUV422_ORDER_MASK);
+
+ if (com_plane_fmt->fmt_index < 0)
+ return -EINVAL;
+
+ memcpy(&com_plane_fmt->gen_pixel_format,
+ &skl_pixel_formats[com_plane_fmt->fmt_index],
+ sizeof(struct pixel_format));
+
+ com_plane_fmt->stride_mask = SKL_PLANE_STRIDE_MASK;
+
+ return 0;
+}
+
+static int intel_vgpu_get_pixel_format(struct intel_vgpu *vgpu,
+ u32 plane_ctl, struct intel_vgpu_common_plane_format *com_plane_fmt,
+ enum intel_gvt_plane_type plane)
+{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+ if (IS_SKYLAKE(dev_priv))
+ return skl_get_pixel_format(plane_ctl, com_plane_fmt, plane);
+ else
+ return gen8_get_pixel_format(plane_ctl, com_plane_fmt, plane); }
+
+static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu,
+ enum intel_gvt_plane_type plane, int pipe, u32 tiled, int stride_mask,
+ int bpp)
+{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ u32 stride_reg = 0;
+ u32 stride = 0;
+
+ if (plane == PRIMARY_PLANE)
+ stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
+ else if (plane == SPRITE_PLANE)
+ stride_reg = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) & stride_mask;
+ else
+ gvt_err("unsupported plane: %d\n", plane);
+
+ stride = stride_reg;
+
+ if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
+ switch (tiled) {
+ case PLANE_CTL_TILED_LINEAR:
+ stride = stride_reg * 64;
+ break;
+
+ case PLANE_CTL_TILED_X:
+ stride = stride_reg * 512;
+ break;
+
+ case PLANE_CTL_TILED_Y:
+ stride = stride_reg * 128;
+ break;
+
+ case PLANE_CTL_TILED_YF:
+ if (bpp == 8)
+ stride = stride_reg * 64;
+ else if (bpp == 16 || bpp == 32 || bpp == 64)
+ stride = stride_reg * 128;
+ else
+ gvt_err("skl: unsupported bpp: %d\n", bpp);
+ break;
+
+ default:
+ gvt_err("skl: unsupported tile format:%x\n", tiled);
+ }
+ }
+
+ return stride;
+}
+
+int intel_vgpu_decode_primary_plane_format(struct intel_vgpu *vgpu, int pipe,
+ struct intel_vgpu_primary_plane_format *plane) {
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ struct intel_vgpu_common_plane_format com_plane_fmt;
+ u32 v;
+
+ v = vgpu_vreg(vgpu, DSPCNTR(pipe));
+ plane->enabled = !!(v & DISPLAY_PLANE_ENABLE);
+ if (!plane->enabled)
+ return 0;
+
+ if (intel_vgpu_get_pixel_format(vgpu, v, &com_plane_fmt,
+ PRIMARY_PLANE)) {
+ gvt_err("get pixel format error.\n");
+ return -EINVAL;
+ }
+
+ if (!com_plane_fmt.gen_pixel_format.bpp) {
+ gvt_err("non-supported pixel format (0x%x)\n",
+ com_plane_fmt.fmt_index);
+ return -EINVAL;
+ }
+
+ plane->tiled = com_plane_fmt.tiled;
+ plane->hw_format = com_plane_fmt.fmt_index;
+ plane->bpp = com_plane_fmt.gen_pixel_format.bpp;
+ plane->drm_format = com_plane_fmt.gen_pixel_format.drm_format;
+ memcpy(plane->drm_fmt_desc, com_plane_fmt.gen_pixel_format.desc,
+ MAX_DRM_STR_SZ);
+
+ plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & GTT_PAGE_MASK;
+ plane->stride = intel_vgpu_get_stride(vgpu, PRIMARY_PLANE, pipe,
+ plane->tiled, com_plane_fmt.stride_mask, plane->bpp);
+ plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe))
+ & _PIPE_H_SRCSZ_MASK) >> _PIPE_H_SRCSZ_SHIFT;
+ plane->width += 1;
+ plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe))
+ & _PIPE_H_SRCSZ_MASK) >> _PIPE_H_SRCSZ_SHIFT;
+ plane->height += 1;
+
+ v = vgpu_vreg(vgpu, DSPTILEOFF(pipe));
+ plane->x_offset = (v & _PRI_PLANE_X_OFF_MASK) >> _PRI_PLANE_X_OFF_SHIFT;
+ plane->y_offset = (v & _PRI_PLANE_Y_OFF_MASK) >>
+_PRI_PLANE_Y_OFF_SHIFT;
+
+ return 0;
+}
+
+int intel_vgpu_decode_sprite_plane_format(struct intel_vgpu *vgpu, int pipe,
+ struct intel_vgpu_sprite_plane_format *plane) {
+ struct intel_vgpu_common_plane_format com_plane_fmt;
+ u32 v;
+
+ v = vgpu_vreg(vgpu, SPRCTL(pipe));
+ plane->enabled = !!(v & SPRITE_ENABLE);
+ if (!plane->enabled)
+ return 0;
+
+ if (intel_vgpu_get_pixel_format(vgpu, v, &com_plane_fmt,
+ SPRITE_PLANE)) {
+ gvt_err("get pixel format error.\n");
+ return -EINVAL;
+ }
+
+ if (!com_plane_fmt.gen_pixel_format.bpp) {
+ gvt_err("non-supported pixel format (0x%x)\n",
+ com_plane_fmt.fmt_index);
+ return -EINVAL;
+ }
+
+ plane->tiled = com_plane_fmt.tiled;
+ plane->hw_format = com_plane_fmt.fmt_index;
+ plane->bpp = com_plane_fmt.gen_pixel_format.bpp;
+ plane->drm_format = com_plane_fmt.gen_pixel_format.drm_format;
+ memcpy(plane->drm_fmt_desc, com_plane_fmt.gen_pixel_format.desc,
+ MAX_DRM_STR_SZ);
+
+ plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & GTT_PAGE_MASK;
+ plane->stride = intel_vgpu_get_stride(vgpu, SPRITE_PLANE, pipe,
+ plane->tiled, com_plane_fmt.stride_mask, plane->bpp);
+
+ v = vgpu_vreg(vgpu, SPRSIZE(pipe));
+ plane->height = (v & _SPRITE_SIZE_HEIGHT_MASK)
+ >> _SPRITE_SIZE_HEIGHT_SHIFT;
+ plane->width = (v & _SPRITE_SIZE_WIDTH_MASK)
+ >> _SPRITE_SIZE_WIDTH_SHIFT;
+ plane->height += 1;
+ plane->width += 1;
+
+ v = vgpu_vreg(vgpu, SPRPOS(pipe));
+ plane->x_pos = (v & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
+ plane->y_pos = (v & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
+
+ v = vgpu_vreg(vgpu, SPROFFSET(pipe));
+ plane->x_offset = (v & _SPRITE_OFFSET_START_X_MASK)
+ >> _SPRITE_OFFSET_START_X_SHIFT;
+ plane->y_offset = (v & _SPRITE_OFFSET_START_Y_MASK)
+ >> _SPRITE_OFFSET_START_Y_SHIFT;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h
new file mode 100644
index 0000000..d3f7b9e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+"Software"),
+ * to deal in the Software without restriction, including without
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+next
+ * paragraph) shall be included in all copies or substantial portions
+of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Kevin Tian <kevin.tian at intel.com<mailto:kevin.tian at intel.com>>
+ *
+ * Contributors:
+ * Ping Gao <ping.a.gao at intel.com<mailto:ping.a.gao at intel.com>>
+ * Xiaoguang Chen <xiaoguang.chen at intel.com<mailto:xiaoguang.chen at intel.com>>
+ * Yang Liu <yang2.liu at intel.com<mailto:yang2.liu at intel.com>>
+ *
+ */
+
+#ifndef _GVT_FB_DECODER_H_
+#define _GVT_FB_DECODER_H_
+
+
+#define MAX_DRM_STR_SZ 50
+struct intel_vgpu_primary_plane_format {
+ u8 enabled;
+ u32 tiled;
+ u8 bpp;
+ u32 hw_format;
+ u32 drm_format;
+ u32 base;
+ u32 x_offset;
+ u32 y_offset;
+ u32 width;
+ u32 height;
+ u32 stride;
+ u8 drm_fmt_desc[MAX_DRM_STR_SZ];
+};
+
+struct intel_vgpu_sprite_plane_format {
+ u8 enabled;
+ u8 tiled;
+ u8 bpp;
+ u32 hw_format;
+ u32 drm_format;
+ u32 base;
+ u32 x_pos;
+ u32 y_pos;
+ u32 x_offset;
+ u32 y_offset;
+ u32 width;
+ u32 height;
+ u32 stride;
+ u8 drm_fmt_desc[MAX_DRM_STR_SZ];
+};
+
+struct pixel_format {
+ int drm_format;
+ int bpp;
+ char *desc;
+};
+
+struct intel_vgpu_common_plane_format {
+ struct pixel_format gen_pixel_format;
+ u32 tiled;
+ int fmt_index;
+ int stride_mask;
+};
+
+int intel_vgpu_decode_primary_plane_format(struct intel_vgpu *vgpu, int pipe,
+ struct intel_vgpu_primary_plane_format *plane); int
+intel_vgpu_decode_sprite_plane_format(struct intel_vgpu *vgpu, int pipe,
+ struct intel_vgpu_sprite_plane_format *plane);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 6dfc48b..0a43b46 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -46,6 +46,7 @@
#include "sched_policy.h"
#include "render.h"
#include "cmd_parser.h"
+#include "fb_decoder.h"
#define GVT_MAX_VGPU 8
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index fbd023a..1233e1f 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -54,6 +54,46 @@
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
+/* primary plane */
+#define _PRI_PLANE_FMT_SHIFT 26
+#define _PRI_PLANE_TILE_SHIFT 10
+
+#define _PRI_PLANE_STRIDE_SHIFT 6
+#define _PRI_PLANE_STRIDE_MASK (0x3ff << _PRI_PLANE_STRIDE_SHIFT)
+#define SKL_PLANE_STRIDE_MASK 0x3ff
+
+#define _PIPE_V_SRCSZ_SHIFT 0
+#define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT) #define
+_PIPE_H_SRCSZ_SHIFT 16 #define _PIPE_H_SRCSZ_MASK (0x1fff <<
+_PIPE_H_SRCSZ_SHIFT)
+
+#define _PRI_PLANE_X_OFF_SHIFT 0
+#define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)
+#define _PRI_PLANE_Y_OFF_SHIFT 16 #define _PRI_PLANE_Y_OFF_MASK (0xfff
+<< _PRI_PLANE_Y_OFF_SHIFT)
+/* sprite */
+#define _SPRITE_FMT_SHIFT 25
+#define _SPRITE_YUV_ORDER_SHIFT 16
+
+#define _SPRITE_STRIDE_SHIFT 6
+#define _SPRITE_STRIDE_MASK (0x1ff << _SPRITE_STRIDE_SHIFT)
+
+#define _SPRITE_POS_X_SHIFT 0
+#define _SPRITE_POS_Y_SHIFT 16
+#define _SPRITE_POS_X_MASK (0x1fff << _SPRITE_POS_X_SHIFT)
+#define _SPRITE_POS_Y_MASK (0xfff << _SPRITE_POS_Y_SHIFT)
+
+#define _SPRITE_SIZE_WIDTH_SHIFT 0
+#define _SPRITE_SIZE_HEIGHT_SHIFT 16
+#define _SPRITE_SIZE_WIDTH_MASK (0x1fff << _SPRITE_SIZE_WIDTH_SHIFT)
+#define _SPRITE_SIZE_HEIGHT_MASK (0xfff << _SPRITE_SIZE_HEIGHT_SHIFT)
+
+#define _SPRITE_OFFSET_START_X_SHIFT 0
+#define _SPRITE_OFFSET_START_Y_SHIFT 16
+#define _SPRITE_OFFSET_START_X_MASK (0x1fff << _SPRITE_OFFSET_START_X_SHIFT)
+#define _SPRITE_OFFSET_START_Y_MASK (0xfff << _SPRITE_OFFSET_START_Y_SHIFT)
+
+
#define _REG_VECS_EXCC 0x1A028
#define _REG_VCS2_EXCC 0x1c028
--
2.7.4
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