[PATCH] drm/i915/gvt: correct mask setting for CSFE_CHICKEN1

[Xinyun Liu]

Hi Zhi, 

Thanks for the review. I'm rebasing the conformance check feature against
v4.18, here is the commits:
https://github.com/projectacrn/acrn-kernel/compare/acrn_rebase_v418...xinyunliu:xyl_rebase_v4.18?expand=1

In Acrn, we currnetly don't save/restore engine mmio for performance concern,
so need to do this kind of check. And it has similiar idea as this commit:

cea9083e35b2 - drm/i915/gvt: Add new debugfs tool mmio_diff (2017-11-16)
<Changbin Du>

-Xinyun
On Wed, Sep 19, 2018 at 01:53:52PM -0400, Zhi Wang wrote:
> Thanks for the patch. BTW: Could you share some information about this
> conformance check test. It looks quite amazing. :)
> 
> Reviewed-by: Zhi Wang <zhi.a.wang at intel.com>
> 
> On 09/19/18 03:28, Xinyun Liu wrote:
> >CSFE_CHICKEN1(0x20d4) needs access with mask. This is caught in AcrnGT
> >conformance check test:
> >
> >[drm:intel_gvt_vgpu_conformance_check]
> >	*ERROR* gvt: vgpu1 unconformance mmio 0x20d4:0x40004,0x4
> >
> >Signed-off-by: Xinyun Liu <xinyun.liu at intel.com>
> >---
> >  drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> >index 10e63eea5492..36a5147cd01e 100644
> >--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> >+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> >@@ -131,7 +131,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> >  	{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
> >  	{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
> >-	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
> >+	{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
> >  	{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
> >  	{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
> >
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