[Intel-xe] [PATCH 11/15] drm/xe/xe2: Add MOCS table

[Matt Roper]

On Fri, Aug 11, 2023 at 09:06:14AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
> 
> Additional minor change to remove L4_2_RESERVED, which will never be
> required.
> 
> Bspec: 71582
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mocs.c | 29 +++++++++++++++++++++++------
>  1 file changed, 23 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index c9653978fc9f5..d779ab8466d32 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -62,13 +62,15 @@ struct xe_mocs_info {
>  #define L3_LKUP(value)		((value) << 7)
>  
>  /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
> -#define _L4_CACHEABILITY	REG_GENMASK(3, 2)
> -#define IG_PAT			REG_BIT(8)
> +#define IG_PAT				REG_BIT(8)
> +#define GLOB_L3_CACHEABILITY_MASK	REG_GENMASK(5, 4)
> +#define L4_CACHEABILITY_MASK		REG_GENMASK(3, 2)

It looks a little bit strange to have "GLOB_" on the L3 but not on the
L4; should we make these two names consistent?  The symbol names
recommended on bspec page 65553 are "L{3,4}_CACHE_POLICY" so maybe we
should just use those names (with "_MASK" on the end) since that won't
clash with the old LNCF define?

Anyway, it's up to you if you think it's worth renaming anything or
not.  All the values look correct so

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

>  
>  /* Helper defines */
>  #define GEN9_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */
>  #define PVC_NUM_MOCS_ENTRIES	3
>  #define MTL_NUM_MOCS_ENTRIES    16
> +#define XE2_NUM_MOCS_ENTRIES	16
>  
>  /* (e)LLC caching options */
>  /*
> @@ -93,10 +95,14 @@ struct xe_mocs_info {
>  #define L3_3_WB			_L3_CACHEABILITY(3)
>  
>  /* L4 caching options */
> -#define L4_0_WB                 REG_FIELD_PREP(_L4_CACHEABILITY, 0)
> -#define L4_1_WT                 REG_FIELD_PREP(_L4_CACHEABILITY, 1)
> -#define L4_2_RESERVED           REG_FIELD_PREP(_L4_CACHEABILITY, 2)
> -#define L4_3_UC                 REG_FIELD_PREP(_L4_CACHEABILITY, 3)
> +#define L4_0_WB                 REG_FIELD_PREP(L4_CACHEABILITY_MASK, 0)
> +#define L4_1_WT                 REG_FIELD_PREP(L4_CACHEABILITY_MASK, 1)
> +#define L4_3_UC                 REG_FIELD_PREP(L4_CACHEABILITY_MASK, 3)
> +
> +#define XE2_L3_0_WB		REG_FIELD_PREP(GLOB_L3_CACHEABILITY_MASK, 0)
> +/* XD: WB Transient Display */
> +#define XE2_L3_1_XD		REG_FIELD_PREP(GLOB_L3_CACHEABILITY_MASK, 1)
> +#define XE2_L3_3_UC		REG_FIELD_PREP(GLOB_L3_CACHEABILITY_MASK, 3)
>  
>  #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
>  	[__idx] = { \
> @@ -370,6 +376,17 @@ static const struct xe_mocs_entry mtl_mocs_desc[] = {
>  		   L3_GLBGO(1) | L3_1_UC),
>  };
>  
> +static const struct xe_mocs_entry xe2_mocs_table[] = {
> +	/* Defer to PAT */
> +	MOCS_ENTRY(0, XE2_L3_0_WB | L4_0_WB, 0),
> +	/* Cached L3 + L4 */
> +	MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
> +	/* Uncached L3, Cached L4 */
> +	MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
> +	/* Uncached L3 + L4 */
> +	MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),
> +};
> +
>  static unsigned int get_mocs_settings(struct xe_device *xe,
>  				      struct xe_mocs_info *info)
>  {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation