[Intel-xe] [PATCH v4 01/31] drm/xe/mtl: Disable media GT

Gustavo Sousa gustavo.sousa at intel.com
Thu Jun 1 15:08:45 UTC 2023


Quoting Matt Roper (2023-05-31 21:03:33-03:00)
>Xe incorrectly conflates the concept of 'tile' and 'GT.'  Since MTL's
>media support is not yet functioning properly, let's just disable it
>completely for now while we fix the fundamental driver design.  Support
>for media GTs on platforms like MTL will be re-added later.
>
>v2:
> - Drop some unrelated code cleanup that didn't belong in this patch.
>   (Lucas)
>v3:
> - Drop unnecessary xe_gt.h include.  (Gustavo)
>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Cc: Gustavo Sousa <gustavo.sousa at intel.com>
>Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
>Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Acked-by: Gustavo Sousa <gustavo.sousa at intel.com>

>---
> drivers/gpu/drm/xe/xe_mmio.c |  2 --
> drivers/gpu/drm/xe/xe_pci.c  | 12 ------------
> 2 files changed, 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
>index d3b57669c9a7..ef2353eef6fe 100644
>--- a/drivers/gpu/drm/xe/xe_mmio.c
>+++ b/drivers/gpu/drm/xe/xe_mmio.c
>@@ -340,8 +340,6 @@ static void xe_mmio_probe_tiles(struct xe_device *xe)
>         mtcfg = xe_mmio_read64(gt, XEHP_MTCFG_ADDR);
>         adj_tile_count = xe->info.tile_count =
>                 REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
>-        if (xe->info.media_verx100 >= 1300)
>-                xe->info.tile_count *= 2;
> 
>         drm_info(&xe->drm, "tile_count: %d, adj_tile_count %d\n",
>                  xe->info.tile_count, adj_tile_count);
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index d8f1213ae1d6..6f0c4203fca3 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -290,21 +290,11 @@ static const struct xe_device_desc pvc_desc = {
>         .extra_gts = pvc_gts,
> };
> 
>-static const struct xe_gt_desc xelpmp_gts[] = {
>-        {
>-                .type = XE_GT_TYPE_MEDIA,
>-                .vram_id = 0,
>-                .mmio_adj_limit = 0x40000,
>-                .mmio_adj_offset = 0x380000,
>-        },
>-};
>-
> static const struct xe_device_desc mtl_desc = {
>         /* .graphics and .media determined via GMD_ID */
>         .require_force_probe = true,
>         PLATFORM(XE_METEORLAKE),
>         .has_display = true,
>-        .extra_gts = xelpmp_gts,
> };
> 
> #undef PLATFORM
>@@ -566,8 +556,6 @@ static int xe_info_init(struct xe_device *xe,
>          * treats it as the number of GTs rather than just the number of tiles.
>          */
>         xe->info.tile_count = 1 + graphics_desc->max_remote_tiles;
>-        if (MEDIA_VER(xe) >= 13)
>-                xe->info.tile_count++;
> 
>         for (id = 0; id < xe->info.tile_count; ++id) {
>                 gt = xe->gt + id;
>-- 
>2.40.1
>


More information about the Intel-xe mailing list