[Intel-xe] ✗ CI.checkpatch: warning for Implement rcs/ccs missing invalidations and flushes

[Patchwork]

== Series Details ==

Series: Implement rcs/ccs missing invalidations and flushes
URL   : https://patchwork.freedesktop.org/series/119033/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c7d32770e3cd31d9fc134ce41f329b10aa33ee15
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e101f891af28a3685c61bb6145a14f4a6db6c87f
Author: Thomas Hellström <thomas.hellstrom at linux.intel.com>
Date:   Wed Jun 7 19:47:29 2023 +0200

    drm/xe: Emit a render cache flush after each rcs/ccs batch
    
    We need to flush render caches before fence signalling, where we might
    release the memory for reuse. We can't rely on userspace doing this,
    so flush render caches after the batch, but before user fence- and
    dma_fence signalling.
    
    Copy the cache flush from i915, but omit PIPE_CONTROL_FLUSH_L3, since it
    should be implied by the other flushes. Also omit
    PIPE_CONTROL_TLB_INVALIDATE since there should be no apparent need to
    invalidate TLB after batch completion.
    
    Signed-off-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
+ /mt/dim checkpatch dc8094ef1ae1faa7bff0a2a3d510a38ba557302a drm-intel
1745dca57 drm/xe: Invalidate TLB also on bind if in scratch page mode
-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/xe/regs/xe_gpu_commands.h:76:
+#define   PIPE_CONTROL_TLB_INVALIDATE                   (1<<18)
                                                           ^

total: 0 errors, 0 warnings, 1 checks, 82 lines checked
e101f891a drm/xe: Emit a render cache flush after each rcs/ccs batch