[Intel-xe] [PATCH] [RFC]drm/xe: Sysfs entries to query fused min, max frequency of lmem

[Matt Roper]

On Tue, Jun 06, 2023 at 01:21:42AM -0700, Sujaritha Sundaresan wrote:
> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h |  7 +++++
>  drivers/gpu/drm/xe/xe_guc_pc.c    | 44 +++++++++++++++++++++++++++++++
>  2 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 8be616a1bd51..bd7b26296402 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -101,4 +101,11 @@
>  #define DSMBASE					XE_REG(0x1080C0)
>  #define   BDSM_MASK				REG_GENMASK64(63, 20)
>  
> +#define   XEHP_PCODE_FREQUENCY_CONFIG           0x6e
> +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_P0      0x0
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_PN      0x1
> +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> +#define     PCODE_MBOX_DOMAIN_HBM               0x2
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 67faa9ee0006..1b349ce74c3d 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -453,6 +453,48 @@ static ssize_t freq_rpn_show(struct device *dev,
>  }
>  static DEVICE_ATTR_RO(freq_rpn);
>  
> +static ssize_t freq_mem_rp0_show(struct device *dev,
> +				 struct device_attribute *attr, char *buff)
> +{
> +	struct kobject *kobj = &dev->kobj;
> +	struct xe_gt *gt = kobj_to_gt(kobj);
> +	u32 val;
> +	int err;
> +
> +	err = xe_pcode_read(dev, XEHPSDV_PCODE_FREQUENCY_CONFIG,

This doesn't match the #define above (XEHPSDV vs XEHP).

> +			    PCODE_MBOX_FC_SC_READ_FUSED_P0,
> +			    PCODE_MBOX_DOMAIN_HBM, &val);
> +	if (err)
> +		return err;
> +
> +	/* data_out - Fused P0 for domain ID in units of 50 MHz */
> +	val *= GT_FREQUENCY_MULTIPLIER;
> +
> +	return sysfs_emit(buff, "%u\n", val);
> +}
> +static DEVICE_ATTR_RO(freq_mem_rp0);
> +
> +static ssize_t freq_mem_rpn_show(struct device *dev,
> +				 struct device_attribute *attr, char *buff)
> +{
> +	struct kobject *kobj = &dev->kobj;
> +	struct xe_gt *gt = kobj_to_gt(kobj);
> +	u32 val;
> +	int err;
> +
> +	err = xe_pcode_read(dev, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> +			    PCODE_MBOX_FC_SC_READ_FUSED_PN,
> +			    PCODE_MBOX_DOMAIN_HBM, &val);
> +	if (err)
> +		return err;
> +
> +	/* data_out - Fused P0 for domain ID in units of 50 MHz */
> +	val *= GT_FREQUENCY_MULTIPLIER;
> +
> +	return sysfs_emit(buff, "%u\n", val);
> +}
> +static DEVICE_ATTR_RO(freq_mem_rpn);
> +
>  static ssize_t freq_min_show(struct device *dev,
>  			     struct device_attribute *attr, char *buf)
>  {
> @@ -631,6 +673,8 @@ static const struct attribute *pc_attrs[] = {
>  	&dev_attr_freq_rp0.attr,
>  	&dev_attr_freq_rpe.attr,
>  	&dev_attr_freq_rpn.attr,
> +	&dev_attr_freq_mem_rp0.attr,
> +	&dev_attr_freq_mem_rpn.attr,

If these are related to LMEM frequency should they be in some other list
that only gets created if we're running on a platform that has LMEM?

For that matter, does it make sense to have LMEM items (which are a
tile-based concept) under a per-GT sysfs?  Or would it make more sense
to have these under a separate per-tile sysfs?


Matt

>  	&dev_attr_freq_min.attr,
>  	&dev_attr_freq_max.attr,
>  	&dev_attr_rc_status.attr,
> -- 
> 2.39.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation