[Intel-xe] [PATCH] [RFC]drm/xe: Sysfs entries to query fused min, max frequency of lmem

[Dixit, Ashutosh]

On Tue, 06 Jun 2023 20:38:34 -0700, Sundaresan, Sujaritha wrote:
>
> > On Jun 6, 2023, at 9:27 PM, Dixit, Ashutosh <ashutosh.dixit at intel.com> wrote:
> >
> > On Tue, 06 Jun 2023 01:21:42 -0700, Sujaritha Sundaresan wrote:
> >>
> >
> > Hi Suja,
> >
> > Once again sysfs_create_files is missing from the patch.
> >
> > Also xe calls lmem vram, so sysfs file names should something like
> > vram_rp0/rpn_freq_mhz, "mem" is too general.
> >
> > Ashutosh
>
> Hi Ashutosh,
>
> Yeah this is not the complete patch. I was hoping to get some feedback on
> the naming and placing of the code.
>
> Thanks for the review. I will rename the attributes to reflect the vram.
>
> Is it okay to leave the code in the current file ? Should the PCODE
> definitions be here or another regs file ?

Not sure whether the vram sysfs functions belong in xe_guc_pc.c, but the
pcode definitions should be in xe_pcode_api.h.

>
> Regards,
> Suja
> >
> >
> >> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan at intel.com>
> >> ---
> >> drivers/gpu/drm/xe/regs/xe_regs.h |  7 +++++
> >> drivers/gpu/drm/xe/xe_guc_pc.c    | 44 +++++++++++++++++++++++++++++++
> >> 2 files changed, 51 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> >> index 8be616a1bd51..bd7b26296402 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> >> @@ -101,4 +101,11 @@
> >> #define DSMBASE                    XE_REG(0x1080C0)
> >> #define   BDSM_MASK                REG_GENMASK64(63, 20)
> >>
> >> +#define   XEHP_PCODE_FREQUENCY_CONFIG           0x6e
> >> +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> >> +#define     PCODE_MBOX_FC_SC_READ_FUSED_P0      0x0
> >> +#define     PCODE_MBOX_FC_SC_READ_FUSED_PN      0x1
> >> +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> >> +#define     PCODE_MBOX_DOMAIN_HBM               0x2
> >> +
> >> #endif
> >> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> >> index 67faa9ee0006..1b349ce74c3d 100644
> >> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> >> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> >> @@ -453,6 +453,48 @@ static ssize_t freq_rpn_show(struct device *dev,
> >> }
> >> static DEVICE_ATTR_RO(freq_rpn);
> >>
> >> +static ssize_t freq_mem_rp0_show(struct device *dev,
> >> +                 struct device_attribute *attr, char *buff)
> >> +{
> >> +    struct kobject *kobj = &dev->kobj;
> >> +    struct xe_gt *gt = kobj_to_gt(kobj);
> >> +    u32 val;
> >> +    int err;
> >> +
> >> +    err = xe_pcode_read(dev, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> >> +                PCODE_MBOX_FC_SC_READ_FUSED_P0,
> >> +                PCODE_MBOX_DOMAIN_HBM, &val);
> >> +    if (err)
> >> +        return err;
> >> +
> >> +    /* data_out - Fused P0 for domain ID in units of 50 MHz */
> >> +    val *= GT_FREQUENCY_MULTIPLIER;
> >> +
> >> +    return sysfs_emit(buff, "%u\n", val);
> >> +}
> >> +static DEVICE_ATTR_RO(freq_mem_rp0);
> >> +
> >> +static ssize_t freq_mem_rpn_show(struct device *dev,
> >> +                 struct device_attribute *attr, char *buff)
> >> +{
> >> +    struct kobject *kobj = &dev->kobj;
> >> +    struct xe_gt *gt = kobj_to_gt(kobj);
> >> +    u32 val;
> >> +    int err;
> >> +
> >> +    err = xe_pcode_read(dev, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> >> +                PCODE_MBOX_FC_SC_READ_FUSED_PN,
> >> +                PCODE_MBOX_DOMAIN_HBM, &val);
> >> +    if (err)
> >> +        return err;
> >> +
> >> +    /* data_out - Fused P0 for domain ID in units of 50 MHz */
> >> +    val *= GT_FREQUENCY_MULTIPLIER;
> >> +
> >> +    return sysfs_emit(buff, "%u\n", val);
> >> +}
> >> +static DEVICE_ATTR_RO(freq_mem_rpn);
> >> +
> >> static ssize_t freq_min_show(struct device *dev,
> >>                 struct device_attribute *attr, char *buf)
> >> {
> >> @@ -631,6 +673,8 @@ static const struct attribute *pc_attrs[] = {
> >>    &dev_attr_freq_rp0.attr,
> >>    &dev_attr_freq_rpe.attr,
> >>    &dev_attr_freq_rpn.attr,
> >> +    &dev_attr_freq_mem_rp0.attr,
> >> +    &dev_attr_freq_mem_rpn.attr,
> >>    &dev_attr_freq_min.attr,
> >>    &dev_attr_freq_max.attr,
> >>    &dev_attr_rc_status.attr,
> >> --
> >> 2.39.1
> >>