[Intel-xe] [PATCH V3 1/3] drm/xe: Add sysfs entry for tile
Iddamsetty, Aravind
aravind.iddamsetty at intel.com
Thu Jun 8 08:08:37 UTC 2023
On 08-06-2023 13:15, Tejas Upadhyay wrote:
> We have recently introduced tile for each gpu,
> so lets add sysfs entry per tile for userspace
> to provide required information specific to tile.
>
> V3:
> - Make API to return void and add drm_warn - Aravind
> V2:
> - Add logs in failure path
>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_device_types.h | 3 ++
> drivers/gpu/drm/xe/xe_tile.c | 3 ++
> drivers/gpu/drm/xe/xe_tile.h | 2 +
> drivers/gpu/drm/xe/xe_tile_sysfs.c | 61 ++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_tile_sysfs.h | 19 ++++++++
> drivers/gpu/drm/xe/xe_tile_sysfs_types.h | 27 +++++++++++
> 7 files changed, 116 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs.c
> create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs.h
> create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index f34d4bdd510b..41a6c0d0dee7 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -98,6 +98,7 @@ xe-y += xe_bb.o \
> xe_step.o \
> xe_sync.o \
> xe_tile.o \
> + xe_tile_sysfs.o \
> xe_trace.o \
> xe_ttm_sys_mgr.o \
> xe_ttm_stolen_mgr.o \
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 17b6b1cc5adb..db61da4d6212 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -150,6 +150,9 @@ struct xe_tile {
>
> /** @migrate: Migration helper for vram blits and clearing */
> struct xe_migrate *migrate;
> +
> + /** @sysfs: sysfs' kobj used by xe_tile_sysfs */
> + struct kobject *sysfs;
> };
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
> index 6414aa810355..ac70486d09c3 100644
> --- a/drivers/gpu/drm/xe/xe_tile.c
> +++ b/drivers/gpu/drm/xe/xe_tile.c
> @@ -10,6 +10,7 @@
> #include "xe_migrate.h"
> #include "xe_sa.h"
> #include "xe_tile.h"
> +#include "xe_tile_sysfs.h"
> #include "xe_ttm_vram_mgr.h"
>
> /**
> @@ -142,6 +143,8 @@ int xe_tile_init_noalloc(struct xe_tile *tile)
> if (IS_ERR(tile->mem.kernel_bb_pool))
> err = PTR_ERR(tile->mem.kernel_bb_pool);
>
> + xe_tile_sysfs_init(tile);
> +
> err_mem_access:
> xe_device_mem_access_put(tile_to_xe(tile));
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_tile.h b/drivers/gpu/drm/xe/xe_tile.h
> index 33bf41292195..782c47f8bd45 100644
> --- a/drivers/gpu/drm/xe/xe_tile.h
> +++ b/drivers/gpu/drm/xe/xe_tile.h
> @@ -6,6 +6,8 @@
> #ifndef _XE_TILE_H_
> #define _XE_TILE_H_
>
> +#include "xe_device_types.h"
is this needed here?
> +
> struct xe_tile;
>
> int xe_tile_alloc(struct xe_tile *tile);
> diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs.c b/drivers/gpu/drm/xe/xe_tile_sysfs.c
> new file mode 100644
> index 000000000000..5c9ebe40e3c3
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tile_sysfs.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include "xe_tile_sysfs.h"
> +
> +#include <linux/kobject.h>
> +#include <linux/sysfs.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "xe_tile.h"
the headers are not properly aligned the local headers should follow the
standard.
> +
> +static void xe_tile_sysfs_kobj_release(struct kobject *kobj)
> +{
> + kfree(kobj);
> +}
> +
> +static struct kobj_type xe_tile_sysfs_kobj_type = {
> + .release = xe_tile_sysfs_kobj_release,
> + .sysfs_ops = &kobj_sysfs_ops,
> +};
> +
> +static void tile_sysfs_fini(struct drm_device *drm, void *arg)
> +{
> + struct xe_tile *tile = arg;
> +
> + kobject_put(tile->sysfs);
> +}
> +
> +void xe_tile_sysfs_init(struct xe_tile *tile)
> +{
> + struct xe_device *xe = tile_to_xe(tile);
> + struct device *dev = xe->drm.dev;
> + struct kobj_tile *kt;
> + int err;
> +
> + kt = kzalloc(sizeof(*kt), GFP_KERNEL);
> + if (!kt)
> + return;
> +
> + kobject_init(&kt->base, &xe_tile_sysfs_kobj_type);
> + kt->tile = tile;
> +
> + err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id);
> + if (err) {
> + kobject_put(&kt->base);
> + drm_warn(&xe->drm, "failed to register TILE sysfs directory, err: %d\n", err);
> + return;
> + }
> +
> + tile->sysfs = &kt->base;
> +
> + err = drmm_add_action_or_reset(&xe->drm, tile_sysfs_fini, tile);
> + if (err) {
> + drm_warn(&xe->drm, "%s: drmm_add_action_or_reset failed, err: %d\n",
> + __func__, err);
> + return;
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs.h b/drivers/gpu/drm/xe/xe_tile_sysfs.h
> new file mode 100644
> index 000000000000..e4f065039eba
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tile_sysfs.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_TILE_SYSFS_H_
> +#define _XE_TILE_SYSFS_H_
> +
> +#include "xe_tile_sysfs_types.h"
> +
> +void xe_tile_sysfs_init(struct xe_tile *tile);
> +
> +static inline struct xe_tile *
> +kobj_to_tile(struct kobject *kobj)
> +{
> + return container_of(kobj, struct kobj_tile, base)->tile;
> +}
> +
> +#endif /* _XE_TILE_SYSFS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs_types.h b/drivers/gpu/drm/xe/xe_tile_sysfs_types.h
> new file mode 100644
> index 000000000000..75906ba11a9e
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tile_sysfs_types.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_TILE_SYSFS_TYPES_H_
> +#define _XE_TILE_SYSFS_TYPES_H_
> +
> +#include <linux/kobject.h>
> +
> +struct xe_tile;
> +
> +/**
> + * struct kobj_tile - A tile's kobject struct that connects the kobject
> + * and the TILE
> + *
> + * When dealing with multiple TILEs, this struct helps to understand which
> + * TILE needs to be addressed on a given sysfs call.
> + */
> +struct kobj_tile {
> + /** @base: The actual kobject */
> + struct kobject base;
> + /** @tile: A pointer to the tile itself */
> + struct xe_tile *tile;
> +};
> +
> +#endif /* _XE_TILE_SYSFS_TYPES_H_ */
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
Thanks,
Aravind.
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