[Intel-xe] ✓ CI.checkpatch: success for Implement missing invalidations and flushes

[Patchwork]

== Series Details ==

Series: Implement missing invalidations and flushes
URL   : https://patchwork.freedesktop.org/series/119124/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c7d32770e3cd31d9fc134ce41f329b10aa33ee15
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0c3c6ae5ba7532c637c953a836f805a86d66ffd3
Author: Thomas Hellström <thomas.hellstrom at linux.intel.com>
Date:   Fri Jun 9 10:58:40 2023 +0200

    drm/xe: Emit a render cache flush after each rcs/ccs batch
    
    We need to flush render caches before fence signalling, where we might
    release the memory for reuse. We can't rely on userspace doing this,
    so flush render caches after the batch, but before user fence- and
    dma_fence signalling.
    
    Copy the cache flush from i915, but omit PIPE_CONTROL_FLUSH_L3, since it
    should be implied by the other flushes. Also omit
    PIPE_CONTROL_TLB_INVALIDATE since there should be no apparent need to
    invalidate TLB after batch completion.
    
    v2:
    - Update Makefile for OOB WA.
    
    Signed-off-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
    Tested-by: José Roberto de Souza <jose.souza at intel.com>
    Reviewed-by: José Roberto de Souza <jose.souza at intel.com> #1
    Reported-by: José Roberto de Souza <jose.souza at intel.com>
    Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/291
    Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/291
+ /mt/dim checkpatch c075cadc4c6d0238556545baab98a63368908404 drm-intel
6d4f2c42a drm/xe: Invalidate TLB also on bind if in scratch page mode
0c3c6ae5b drm/xe: Emit a render cache flush after each rcs/ccs batch