[Intel-xe] [PATCH v2 0/2] Implement missing invalidations and flushes

[Souza, Jose]

On Fri, 2023-06-09 at 10:58 +0200, Thomas Hellström wrote:
> Mesa is seeing unexpected content in some tests.
> Fixing those require a TLB invalidation at batch start and a
> render cache flush at batch end.
> 
> KMD also requires the latter to make sure any GPU side caches are
> flushed before handing memory over for reuse. This is implemented
> in patch 2.
> 
> The former is likely due to scratch PTEs remaining in the TLB after a
> prefetch or similar. We could discuss whether user-space should be
> responsible for a TLB invalidation after a VM_BIND operation, but
> patch 1 implements a TLB flush at batch start for non-LR vms with scratch
> pages. For LR vms with scratch pages the TLB flush is incoporated
> in the bind fence.
> 
> The TLB invalidation can be optimized / coalesced later.
> 
> 
> Thomas Hellström (2):
>   drm/xe: Invalidate TLB also on bind if in scratch page mode
>   drm/xe: Emit a render cache flush after each rcs/ccs batch

new version tested.

Tested-by: José Roberto de Souza <jose.souza at intel.com>

> 
>  drivers/gpu/drm/xe/Makefile               |  2 +-
>  drivers/gpu/drm/xe/regs/xe_gpu_commands.h |  4 ++
>  drivers/gpu/drm/xe/xe_pt.c                | 17 ++++-
>  drivers/gpu/drm/xe/xe_ring_ops.c          | 82 ++++++++++++++++++++---
>  drivers/gpu/drm/xe/xe_vm.c                |  2 +
>  drivers/gpu/drm/xe/xe_vm_types.h          |  3 +
>  drivers/gpu/drm/xe/xe_wa_oob.rules        |  1 +
>  7 files changed, 97 insertions(+), 14 deletions(-)
>