[Intel-xe] [PATCH v11 08/12] drm/xe/mmio: enforce xe_device_assert_mem_access

Matthew Brost matthew.brost at intel.com
Mon Jun 12 18:17:57 UTC 2023


On Mon, Jun 12, 2023 at 06:12:21PM +0100, Matthew Auld wrote:
> The mem_access is meant to cover any kind of device level memory
> access, mmio included.
> 
> Suggested-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>

Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_mmio.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 3c547d78afba..1a6f0fa9e04e 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -10,6 +10,7 @@
>  #include <linux/io-64-nonatomic-lo-hi.h>
>  
>  #include "regs/xe_reg_defs.h"
> +#include "xe_device.h"
>  #include "xe_device_types.h"
>  #include "xe_gt_types.h"
>  
> @@ -25,6 +26,8 @@ static inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
>  
> +	xe_device_assert_mem_access(tile->xe);
> +
>  	if (reg.addr < gt->mmio.adj_limit)
>  		reg.addr += gt->mmio.adj_offset;
>  
> @@ -36,6 +39,8 @@ static inline void xe_mmio_write32(struct xe_gt *gt,
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
>  
> +	xe_device_assert_mem_access(tile->xe);
> +
>  	if (reg.addr < gt->mmio.adj_limit)
>  		reg.addr += gt->mmio.adj_offset;
>  
> @@ -46,6 +51,8 @@ static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
>  
> +	xe_device_assert_mem_access(tile->xe);
> +
>  	if (reg.addr < gt->mmio.adj_limit)
>  		reg.addr += gt->mmio.adj_offset;
>  
> @@ -69,6 +76,8 @@ static inline void xe_mmio_write64(struct xe_gt *gt,
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
>  
> +	xe_device_assert_mem_access(tile->xe);
> +
>  	if (reg.addr < gt->mmio.adj_limit)
>  		reg.addr += gt->mmio.adj_offset;
>  
> @@ -79,6 +88,8 @@ static inline u64 xe_mmio_read64(struct xe_gt *gt, struct xe_reg reg)
>  {
>  	struct xe_tile *tile = gt_to_tile(gt);
>  
> +	xe_device_assert_mem_access(tile->xe);
> +
>  	if (reg.addr < gt->mmio.adj_limit)
>  		reg.addr += gt->mmio.adj_offset;
>  
> -- 
> 2.40.1
> 


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