[Intel-xe] [PATCH] drm/xe/mtl: Add some initial MTL workarounds

[Sripada, Radhakrishna]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Thursday, June 8, 2023 11:12 AM
> To: intel-xe at lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper at intel.com>
> Subject: [Intel-xe] [PATCH] drm/xe/mtl: Add some initial MTL workarounds
> 
> This adds a handful of workarounds that apply to production steppings of
> MTL:
>  - Wa_14018575942
>  - Wa_22016670082
>  - Wa_14017856879
>  - Wa_18019271663
> 
> Wa_22016670082 is currently only applied to the primary GT at the
> moment, but may need to be extended to the media GT in the future if a
> pending update to the workaround database gets finalized.
> 
> OOB workarounds will need to be implemented separately in future patches
> for Wa_14016712196, Wa_16018063123, and Wa_18013179988.
> 
LGTM,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>

--Radhakrishna(RK) Sripada
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  8 +++++++
>  drivers/gpu/drm/xe/xe_wa.c           | 31 ++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 0f920175526e..3f664011eaea 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -133,6 +133,9 @@
>  #define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4,
> XE_REG_OPTION_MASKED)
>  #define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
> 
> +#define SQCNT1					XE_REG_MCR(0x8718)
> +#define   ENFORCE_RAR				REG_BIT(23)
> +
>  #define XEHP_SQCM				XE_REG_MCR(0x8724)
>  #define   EN_32B_ACCESS				REG_BIT(30)
> 
> @@ -268,7 +271,9 @@
>  #define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
>  #define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
>  #define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
> +#define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
>  #define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
> +#define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
>  #define   FORCE_MISS_FTLB			REG_BIT(3)
> 
>  #define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
> @@ -302,6 +307,9 @@
>  #define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
>  #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP
> 	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
> 
> +#define ROW_CHICKEN3				XE_REG_MCR(0xe49c,
> XE_REG_OPTION_MASKED)
> +#define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
> +
>  #define ROW_CHICKEN				XE_REG_MCR(0xe4f0,
> XE_REG_OPTION_MASKED)
>  #define   UGM_BACKUP_MODE			REG_BIT(13)
>  #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index e5b3ff669465..5eaa9bed9d12 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -236,6 +236,22 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
> GRAPHICS_STEP(A0, B0)),
>  	  XE_RTP_ACTIONS(CLR(MISCCPCTL,
> DOP_CLOCK_GATE_RENDER_ENABLE))
>  	},
> +	{ XE_RTP_NAME("14018575942"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
> +	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
> +			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
> +	},
> +	{ XE_RTP_NAME("22016670082"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
> +	  XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
> +	},
> +
> +	/* Xe_LPM+ */
> +	{ XE_RTP_NAME("14018575942"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1300)),
> +	  XE_RTP_ACTIONS(SET(XELPMP_VDBX_MOD_CTRL,
> FORCE_MISS_FTLB),
> +			 SET(XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
> +	},
> 
>  	{}
>  };
> @@ -502,6 +518,14 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  		       GRAPHICS_STEP(B0, C0)),
>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
>  	},
> +
> +	/* Xe_LPG */
> +	{ XE_RTP_NAME("14017856879"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
> +	},
> +
>  	{}
>  };
> 
> @@ -580,6 +604,13 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> MSAA_OPTIMIZATION_REDUC_DISABLE))
>  	},
> +
> +	/* Xe_LPG */
> +	{ XE_RTP_NAME("18019271663"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
> +	  XE_RTP_ACTIONS(SET(CACHE_MODE_1,
> MSAA_OPTIMIZATION_REDUC_DISABLE))
> +	},
> +
>  	{}
>  };
> 
> --
> 2.40.1