[Intel-xe] [PATCH 2/2] drm/xe/mtl: Add support to get C6 residency/status of MTL
Nilawar, Badal
badal.nilawar at intel.com
Thu Jun 15 09:00:00 UTC 2023
Hi Anshuman,
On 14-06-2023 13:38, Gupta, Anshuman wrote:
>
>
>> -----Original Message-----
>> From: Tauro, Riana <riana.tauro at intel.com>
>> Sent: Tuesday, June 13, 2023 2:17 PM
>> To: intel-xe at lists.freedesktop.org
>> Cc: Tauro, Riana <riana.tauro at intel.com>; Gupta, Anshuman
>> <anshuman.gupta at intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com>;
>> Belgaumkar, Vinay <vinay.belgaumkar at intel.com>; Dixit, Ashutosh
>> <ashutosh.dixit at intel.com>; Nilawar, Badal <badal.nilawar at intel.com>;
>> Brost, Matthew <matthew.brost at intel.com>; andi.shyti at linux.intel.com;
>> joonas.lahtinen at linux.intel.com
>> Subject: [PATCH 2/2] drm/xe/mtl: Add support to get C6 residency/status of
>> MTL
>>
>> From: Badal Nilawar <badal.nilawar at intel.com>
>>
>> Add the registers to get C6 residency of MTL SAMedia and
>> C6 status of MTL gts
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar at intel.com>
>> Signed-off-by: Riana Tauro <riana.tauro at intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
>> drivers/gpu/drm/xe/xe_gt_idle_sysfs.c | 16 +++++++---
>> drivers/gpu/drm/xe/xe_guc_pc.c | 44
>> +++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_guc_pc.h | 2 ++
>> 4 files changed, 60 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 0f920175526e..7c3dd0a81b71 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -341,6 +341,8 @@
>> #define FORCEWAKE_USER BIT(1)
>> #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
>>
>> +#define MTL_MEDIA_MC6 XE_REG(0x138048)
> Reg should define in a header.
Its already under the header.
>> +
>> #define GT_CORE_STATUS XE_REG(0x138060)
>> #define RCN_MASK REG_GENMASK(2, 0)
>> #define GT_RC0 0
>> diff --git a/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
>> b/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
>> index 1b2dcac46479..a75816a610ae 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
>> @@ -140,11 +140,19 @@ int xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle)
>> if (!kobj)
>> return -ENOMEM;
>>
>> - sprintf(gtidle->name, "gt%d-rc\n", gt->info.id);
>> - /* Multiplier for RC6 Residency counter in units of 1.28us */
>> + if (xe->info.platform == XE_METEORLAKE &&
>> + gt->info.type == XE_GT_TYPE_MEDIA) {
>> + sprintf(gtidle->name, "gt%d-mc\n", gt->info.id);
>> + gtidle->idle_residency = xe_guc_pc_mc6_residency;
>> + gtidle->idle_status = xe_guc_pc_mc_status;
>> + } else {
>> + sprintf(gtidle->name, "gt%d-rc\n", gt->info.id);
>> + gtidle->idle_residency = xe_guc_pc_rc6_residency;
>> + gtidle->idle_status = xe_guc_pc_rc_status;
>> + }
>> +
>> + /* Multiplier for Residency counter in units of 1.28us */
>> gtidle->residency_multiplier = 1280;
>> - gtidle->idle_residency = xe_guc_pc_rc6_residency;
>> - gtidle->idle_status = xe_guc_pc_rc_status;
>>
>> err = sysfs_create_files(kobj, gt_idle_attrs);
>> if (err) {
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
>> b/drivers/gpu/drm/xe/xe_guc_pc.c index 72f49808918a..35ca4115dc96
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -36,6 +36,10 @@
>>
>> #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
> Need Bspec index here.
Will add bspec index to commit message.
>> #define MTL_CAGF_MASK REG_GENMASK(8, 0)
>> +#define MTL_CC_MASK REG_GENMASK(12, 9)
>> +#define MTL_C0 0
>> +#define MTL_C6 3
> These register definition also should move in to the appropriate reg header file
Sure, will move this to reg header file.
>> +
>>
>> #define GT_FREQUENCY_MULTIPLIER 50
>> #define GEN9_FREQ_SCALER 3
>> @@ -598,6 +602,29 @@ enum xe_gt_idle_state xe_guc_pc_rc_status(struct
>> xe_guc_pc *pc)
>> }
>> }
>>
>> +/**
>> + * xe_guc_pc_mc_status - get the current Media C state
>> + * @pc: XE_GuC_PC instance
>> + */
>> +enum xe_gt_idle_state xe_guc_pc_mc_status(struct xe_guc_pc *pc) {
>> + struct xe_gt *gt = pc_to_gt(pc);
>> + u32 reg;
>> +
>> + xe_device_mem_access_get(gt_to_xe(gt));
>> + reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
>> + xe_device_mem_access_put(gt_to_xe(gt));
> Duplication code of getting a wakeref can be avoided with macro.
Agreed but with respect to this series there is not much ROI as only
couple of regs will be benifited from this. Lets keep it simple.
> Thanks,
> Anshuman Gupta.
>> +
>> + switch (REG_FIELD_GET(MTL_CC_MASK, reg)) {
>> + case MTL_C6:
>> + return GT_IDLE_C6;
>> + case MTL_C0:
>> + return GT_IDLE_C0;
>> + default:
>> + return GT_IDLE_UNKNOWN;
>> + }
>> +}
>> +
>> /**
>> * xe_guc_pc_rc6_residency - rc6 residency counter
>> * @pc: Xe_GuC_PC instance
>> @@ -615,6 +642,23 @@ u64 xe_guc_pc_rc6_residency(struct xe_guc_pc
>> *pc)
>> return reg;
>> }
>>
>> +/**
>> + * xe_guc_pc_mc6_residency - mc6 residency counter
>> + * @pc: Xe_GuC_PC instance
>> + */
>> +u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc) {
>> + struct xe_gt *gt = pc_to_gt(pc);
>> + u64 reg;
>> +
>> + xe_device_mem_access_get(gt_to_xe(gt));
>> +
>> + reg = xe_mmio_read32(gt, MTL_MEDIA_MC6);
>> +
>> + xe_device_mem_access_put(gt_to_xe(gt));
>> + return reg;
>> +}
>> +
>> static const struct attribute *pc_attrs[] = {
>> &dev_attr_freq_act.attr,
>> &dev_attr_freq_cur.attr,
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h
>> b/drivers/gpu/drm/xe/xe_guc_pc.h index 976179dbc9a8..0d13c19b7b78
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
>> @@ -13,5 +13,7 @@ int xe_guc_pc_start(struct xe_guc_pc *pc); int
>> xe_guc_pc_stop(struct xe_guc_pc *pc);
>>
>> enum xe_gt_idle_state xe_guc_pc_rc_status(struct xe_guc_pc *pc);
>> +enum xe_gt_idle_state xe_guc_pc_mc_status(struct xe_guc_pc *pc);
>> u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc);
>> +u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
>> #endif /* _XE_GUC_PC_H_ */
>> --
>> 2.40.0
>
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