[Intel-xe] [PATCH v2 2/2] drm/xe/mtl: Add support to get C6 residency/status of MTL
Gupta, Anshuman
anshuman.gupta at intel.com
Fri Jun 16 10:58:17 UTC 2023
> -----Original Message-----
> From: Tauro, Riana <riana.tauro at intel.com>
> Sent: Friday, June 16, 2023 2:55 PM
> To: intel-xe at lists.freedesktop.org
> Cc: Tauro, Riana <riana.tauro at intel.com>; Gupta, Anshuman
> <anshuman.gupta at intel.com>; Belgaumkar, Vinay
> <vinay.belgaumkar at intel.com>; Dixit, Ashutosh
> <ashutosh.dixit at intel.com>; Nilawar, Badal <badal.nilawar at intel.com>;
> andi.shyti at linux.intel.com; Brost, Matthew <matthew.brost at intel.com>;
> joonas.lahtinen at linux.intel.com
> Subject: [PATCH v2 2/2] drm/xe/mtl: Add support to get C6 residency/status
> of MTL
>
> From: Badal Nilawar <badal.nilawar at intel.com>
>
> Add the registers to get C6 residency of MTL SAMedia and
> C6 status of MTL gts
>
> v2:
> - move register definitions to regs header (Anshuman)
> - correct reg definition for mtl rc status
> - make idle_status function common (Badal)
>
> Bspec: 66300
Please remove this space.
>
> Signed-off-by: Badal Nilawar <badal.nilawar at intel.com>
> Signed-off-by: Riana Tauro <riana.tauro at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 11 +++++--
> drivers/gpu/drm/xe/xe_gt_idle_sysfs.c | 15 +++++++---
> drivers/gpu/drm/xe/xe_guc_pc.c | 42 ++++++++++++++++++++-------
> drivers/gpu/drm/xe/xe_guc_pc.h | 3 +-
> 4 files changed, 54 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 3f664011eaea..d654f3311351 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -16,6 +16,11 @@
> #define MEDIA_GT_GSI_OFFSET 0x380000
> #define MEDIA_GT_GSI_LENGTH 0x40000
>
> +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> +#define MTL_MIRROR_TARGET_WP1
> XE_REG(0xc60)
> +#define MTL_CAGF_MASK
> REG_GENMASK(8, 0)
> +#define MTL_CC_MASK
> REG_GENMASK(12, 9)
> +
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0
> XE_REG(0xd00)
> #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
> REG_GENMASK(5, 3)
> @@ -349,10 +354,12 @@
> #define FORCEWAKE_USER BIT(1)
> #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
>
> +#define MTL_MEDIA_MC6 XE_REG(0x138048)
> +
> #define GT_CORE_STATUS XE_REG(0x138060)
> #define RCN_MASK REG_GENMASK(2, 0)
> -#define GT_RC0 0
> -#define GT_RC6 3
> +#define GT_C0 0
> +#define GT_C6 3
>
> #define GT_GFX_RC6_LOCKED XE_REG(0x138104)
> #define GT_GFX_RC6 XE_REG(0x138108)
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
> b/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
> index ec77349dea76..1a1016ff3735 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle_sysfs.c
> @@ -142,11 +142,18 @@ void xe_gt_idle_sysfs_init(struct xe_gt_idle
> *gtidle)
> return;
> }
>
> - sprintf(gtidle->name, "gt%d-rc\n", gt->info.id);
> - /* Multiplier for RC6 Residency counter in units of 1.28us */
> + if (xe->info.platform == XE_METEORLAKE &&
> + gt->info.type == XE_GT_TYPE_MEDIA) {
Hi Badal,
Do we need MTL specific check here, gt->info.type is not sufficient?
that will scale this condition for future platform as well.
> + sprintf(gtidle->name, "gt%d-mc\n", gt->info.id);
> + gtidle->idle_residency = xe_guc_pc_mc6_residency;
> + } else {
> + sprintf(gtidle->name, "gt%d-rc\n", gt->info.id);
> + gtidle->idle_residency = xe_guc_pc_rc6_residency;
> + }
> +
/snip
> {
> struct xe_gt *gt = pc_to_gt(pc);
> - u32 reg;
> + u32 reg, gt_c_state;
>
> xe_device_mem_access_get(gt_to_xe(gt));
> - reg = xe_mmio_read32(gt, GT_CORE_STATUS);
> +
> + if (gt_to_xe(gt)->info.platform == XE_METEORLAKE) {
Similarly can't we check gt->info.type here in order to scale this condition for future
platform ?
Br,
Anshuman Gupta.
> + reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
> + gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);
> + } else {
> + reg = xe_mmio_read32(gt, GT_CORE_STATUS);
> + gt_c_state = REG_FIELD_GET(RCN_MASK, reg);
> + }
> +
> xe_device_mem_access_put(gt_to_xe(gt));
>
> - switch (REG_FIELD_GET(RCN_MASK, reg)) {
> - case GT_RC6:
> + switch (gt_c_state) {
> + case GT_C6:
> return GT_IDLE_C6;
> - case GT_RC0:
> + case GT_C0:
> return GT_IDLE_C0;
> default:
> return GT_IDLE_UNKNOWN;
> @@ -607,6 +612,23 @@ u64 xe_guc_pc_rc6_residency(struct xe_guc_pc
> *pc)
> return reg;
> }
>
> +/**
> + * xe_guc_pc_mc6_residency - mc6 residency counter
> + * @pc: Xe_GuC_PC instance
> + */
> +u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc) {
> + struct xe_gt *gt = pc_to_gt(pc);
> + u64 reg;
> +
> + xe_device_mem_access_get(gt_to_xe(gt));
> +
> + reg = xe_mmio_read32(gt, MTL_MEDIA_MC6);
> +
> + xe_device_mem_access_put(gt_to_xe(gt));
> + return reg;
> +}
> +
> static const struct attribute *pc_attrs[] = {
> &dev_attr_freq_act.attr,
> &dev_attr_freq_cur.attr,
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h
> b/drivers/gpu/drm/xe/xe_guc_pc.h index 976179dbc9a8..370353a40a17
> 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -12,6 +12,7 @@ int xe_guc_pc_init(struct xe_guc_pc *pc); int
> xe_guc_pc_start(struct xe_guc_pc *pc); int xe_guc_pc_stop(struct
> xe_guc_pc *pc);
>
> -enum xe_gt_idle_state xe_guc_pc_rc_status(struct xe_guc_pc *pc);
> +enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc);
> u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc);
> +u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
> #endif /* _XE_GUC_PC_H_ */
> --
> 2.40.0
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