[Intel-xe] [PATCH V4 0/3] drm/xe: Add sysfs entry for tile and relate it to GTs

[Tejas Upadhyay]

With the separation of xe_tile and xe_gt, We now consider
a PCI device (xe_device) to contain one or more tiles (struct xe_tile).
Each tile will contain one or more GTs (struct xe_gt).

Sysfs entries also needs to be aligned as follows:

drm/xe: Add sysfs entry per tile - Adds tile sysfs infrastructure
drm/xe: Add GTs under respective tile sysfs - Relates GTs to each tile
sysfs
drm/xe: Add sysfs entry to report per tile memory size - Reports actual
physical memory per respective tile

Sysfs entries will be as follows:
cat /sys/class/drm/card1/device/tileN/physical_vram_size_bytes

V4 :
   - %s/addr_range/physical_vram_size_byes, make it
     user readable name - Joonas/Aravind
   - Display in bytes - Joonas/Aravind
   - Reorder headers and modify s/LMEM/VRAM - Matt/Aravind
V3 :
   - Make tile_sysfs_init return void and warn for errors
   - Exclude DG1 as it does not have TILE_ADDR_RANGE reg
   - Use sysfs_create_files -> sysfs_create_file
V2 :
   - Address review comments

Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

Tejas Upadhyay (3):
  drm/xe: Add sysfs entry for tile
  drm/xe: Add GTs under respective tile sysfs
  drm/xe: Add sysfs entry to report per tile memory size

 drivers/gpu/drm/xe/Makefile              |  1 +
 drivers/gpu/drm/xe/xe_device_types.h     |  9 +++
 drivers/gpu/drm/xe/xe_gt_sysfs.c         |  4 +-
 drivers/gpu/drm/xe/xe_mmio.c             |  1 +
 drivers/gpu/drm/xe/xe_tile.c             |  3 +
 drivers/gpu/drm/xe/xe_tile.h             |  2 +
 drivers/gpu/drm/xe/xe_tile_sysfs.c       | 78 ++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_tile_sysfs.h       | 19 ++++++
 drivers/gpu/drm/xe/xe_tile_sysfs_types.h | 27 ++++++++
 9 files changed, 142 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs.c
 create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs.h
 create mode 100644 drivers/gpu/drm/xe/xe_tile_sysfs_types.h

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2.25.1