[Intel-xe] [PATCH] drm/xe/huc: Load HuC on Alderlake P and Alderlake S

[Lucas De Marchi]

On Mon, Mar 13, 2023 at 04:11:20PM -0700, Anusha Srivatsa wrote:
>Extending HUC loading support on more platforms.

need to mention here that ADL-S and ADL-P are reusing the TGL firmware
blob.


>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
>---
> drivers/gpu/drm/xe/xe_uc_fw.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>index ff94eec9cafe..5a28ec79fb9d 100644
>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>@@ -51,8 +51,10 @@ static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw)
> 	fw_def(TIGERLAKE,    0, guc_def(tgl,  70, 5, 2))
>
> #define XE_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
>-	fw_def(DG1,          0, huc_def(dg1,  7, 9, 3)) \
>-	fw_def(TIGERLAKE,    0, huc_def(tgl,  7, 9, 3))
>+	fw_def(DG1,            0, huc_def(dg1,  7, 9, 3)) \
>+	fw_def(TIGERLAKE,      0, huc_def(tgl,  7, 9, 3)) \
>+	fw_def(ALDERLAKE_P,    0, huc_def(tgl,  7, 9, 3)) \
>+	fw_def(ALDERLAKE_S,    0, huc_def(tgl,  7, 9, 3))

Looking at upstream firmware repo, we already have
i915/tgl_huc.bin and i915/dg1_huc.bin. Let's follow the upstream
guideline here and strip out the version.

Contrary to i915, as we don't have any baggage about previously
supported firmware version, I don't think we need any fallback
mechanism.

Were you able to test this patch on ADL?

With the additional commit message,

	Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

thanks
Lucas De Marchi

>
> #define __MAKE_UC_FW_PATH_MAJOR(prefix_, name_, major_) \
> 	"xe/" \
>-- 
>2.25.1
>