[Intel-xe] [PATCH v3 13/14] drm/xe: Add missing LRC workarounds for graphics 1200

[Matt Roper]

On Mon, Mar 13, 2023 at 05:30:11PM -0700, Lucas De Marchi wrote:
> Synchronize LRC workarounds for graphics version 1200 with i915 up to
> commit 7cdae9e9ee5e ("drm/i915: Move DG2 tuning to the right function").
> These were probably missed for TGL/RKL before because in i915 it uses a
> !IS_DG1() condition.  Avoid a similar issue by just checking the
> graphics version 1200 since DG1 is 1210.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

for the changes here.  However on the topic of LRC workarounds, it looks
like commit 6d4750630a27b ("drm/xe: Fix duplicated setting for register
0x6604") was incorrect and should probably be reverted.  That patch
moved a real workaround (handling of GS_TIMER) into the tuning function,
but dropped the tuning setting (handling of TDS timer).  The workaround
and tuning setting are updating disjoint bitfields of the register;
they're not equivalent.


Matt

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_wa.c           | 10 ++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 4a7ce09d6b60..4ab7860db9f2 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -98,10 +98,14 @@
>  
>  #define HIZ_CHICKEN				_MMIO(0x7018)
>  #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
> +#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE	REG_BIT(13)
>  
>  /* GEN7 chicken */
>  #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
>  
> +#define COMMON_SLICE_CHICKEN4			_MMIO(0x7300)
> +#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
> +
>  #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
>  #define XEHP_COMMON_SLICE_CHICKEN3		MCR_REG(0x7304)
>  #define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index e21c7ec53b2f..59d2daab5929 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -536,6 +536,16 @@ static const struct xe_rtp_entry lrc_was[] = {
>  				   GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
>  				   XE_RTP_ACTION_FLAG(MASKED_REG)))
>  	},
> +	{ XE_RTP_NAME("1806527549"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> +	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE,
> +			     XE_RTP_ACTION_FLAG(MASKED_REG)))
> +	},
> +	{ XE_RTP_NAME("1606376872"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> +	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC,
> +			     XE_RTP_ACTION_FLAG(MASKED_REG)))
> +	},
>  
>  	/* DG1 */
>  
> -- 
> 2.39.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation