[Intel-xe] [PATCH 1/4] drm/xe/guc: Read HXG fields from DW1 of G2H response

[Michal Wajdeczko]

On 28.03.2023 23:09, Matthew Brost wrote:
> The HXG fields are DW1 not DW0, fix this.

the problem is (was) that some of new Xe CTB code is not correctly
distinguishing between the CTB message (transport layer) and HXG message
(payload of CTB, actual H2G/G2H message)

note that all HXG actions definitions describe HXG messages that start
at DW0 (hence MSG_0, MSG_1 and so on)

thus using:

	FIELD_GET(GUC_HXG_xxx_MSG_0_yyy, msg[1]);

seems just wrong and better to be replaced with:

	FIELD_GET(GUC_HXG_xxx_MSG_0_yyy, hxg[0]);

where:

	u32 *hxg = ctb_msg + GUC_CTB_MSG_MIN_LEN;

> 
> Signed-off-by: Matthew Brost <matthew.brost at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ct.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 5e00b75d3ca2..e5ed9022a0a2 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -783,13 +783,13 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)
>  	if (type == GUC_HXG_TYPE_RESPONSE_FAILURE) {
>  		g2h_fence->fail = true;
>  		g2h_fence->error =
> -			FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, msg[0]);
> +			FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, msg[1]);
>  		g2h_fence->hint =
> -			FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, msg[0]);
> +			FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, msg[1]);
>  	} else if (type == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
>  		g2h_fence->retry = true;
>  		g2h_fence->reason =
> -			FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, msg[0]);
> +			FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, msg[1]);
>  	} else if (g2h_fence->response_buffer) {
>  		g2h_fence->response_len = response_len;
>  		memcpy(g2h_fence->response_buffer, msg + GUC_CTB_MSG_MIN_LEN,