[Intel-xe] [PATCH v3 2/2] drm/xe: Set default MOCS value for copy cs instructions

[Matt Roper]

On Wed, May 03, 2023 at 09:30:13AM -0700, José Roberto de Souza wrote:
> copy cs instructions that dont have a explict MOCS field will use this
> default MOCS value.
> 
> This was mainly copied from i915 source code.
> 
> v2:
> - move to xe_hw_engine.c
> - remove BLIT_CCTL auxiliary macros
> - removed MASKED_REG
> 
> v3:
> - rebased
> 
> BSpec: 45807
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  6 ++++++
>  drivers/gpu/drm/xe/xe_hw_engine.c        | 16 ++++++++++++++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 717d560626cec..b0ba56342773a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -58,6 +58,12 @@
>  
>  #define RING_BBADDR(base)			XE_REG((base) + 0x140)
>  #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
> +
> +/* Same handling MOCS value handling done in RING_CMD_CCTL */
> +#define BLIT_CCTL(base)				XE_REG((base) + 0x204)
> +#define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)
> +#define   BLIT_CCTL_SRC_MOCS_MASK		REG_GENMASK(6, 1)
> +
>  #define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)
>  #define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)
>  
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index d497f0289c372..284b153cd30b5 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -277,6 +277,8 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  	const u8 mocs_read_idx = gt->mocs.uc_index;
>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
>  			        REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
> +	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
> +			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
>  	const struct xe_rtp_entry engine_was[] = {
>  		/*
>  		 * RING_CMD_CCTL specifies the default MOCS entry that will be
> @@ -295,6 +297,20 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  					   ring_cmd_cctl_val,
>  					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  		},
> +		/*
> +		 * Some blitter commands do not have a field for MOCS, those
> +		 * commands will use MOCS index pointed by BLIT_CCTL.
> +		 * BLIT_CCTL registers are needed to be programmed to un-cached.
> +		 */
> +		{ XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
> +		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
> +			       ENGINE_CLASS(COPY)),
> +		  XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
> +				 BLIT_CCTL_DST_MOCS_MASK |
> +				 BLIT_CCTL_SRC_MOCS_MASK,
> +				 blit_cctl_val,
> +				 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> +		},

Unlike CMD_CCTL, we can't put this one on hwe->reg_sr since the
BLIT_CCTL register is part of the context image (bspec 45584, offset
0x44).  We need to get this one onto hwe->reg_lrc instead so that it
gets applied to the golden context image properly.

Regarding my suggestion last time to make this userspace's
responsibility, I thought about it a bit more and it might be best to
have the kernel always apply the uncached MOCS index.  But upgrading to
WB cache behavior (when running on a platform where it's recommended,
and where userspace wants to opt in) is something we can leave to
userspace to handle.  I.e., we always provide the default, safe behavior
and userspace can decide if/when it makes sense to optimize.


Matt

>  		{}
>  	};
>  
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation