[Intel-xe] [PATCH 1/2] drm/xe: Reorder GuC interrupt register definition

[Matt Roper]

On Fri, May 19, 2023 at 06:59:26PM +0200, Michal Wajdeczko wrote:
> We aim to have all definitions sorted by register address.

It seems like there's a lot of things in this header that still don't
follow the convention we're trying to standardize on:
 - A bunch of other registers near the top are still mis-sorted.
 - Some registers are using uppercase hex for the register offsets
   rather than the more widely-used lowercase hex.
 - The definition values are indented different amounts.  I think when
   we started cleaning up these register headers we picked column 49
   (via tabs) as the usual starting point for the values.
 - There's a 'struct guc_doorbell_info' and GUC_NUM_DOORBELLS that don't
   seem to be used anywhere in the driver (and probably wouldn't belong
   in a register header anyway).

Rather than just moving this one register, should we do all of those
updates?


Matt

> 
> Bspec: 49813
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_guc_regs.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> index b4f27cadb68f..f08966c2be20 100644
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -89,7 +89,6 @@
>  
>  #define GUC_SEND_INTERRUPT			XE_REG(0xc4c8)
>  #define   GUC_SEND_TRIGGER			REG_BIT(0)
> -#define GUC_HOST_INTERRUPT			XE_REG(0x1901f0)
>  
>  #define GUC_NUM_DOORBELLS			256
>  
> @@ -116,6 +115,8 @@ struct guc_doorbell_info {
>  #define GUC_WD_VECS_IER				XE_REG(0xC558)
>  #define GUC_PM_P24C_IER				XE_REG(0xC55C)
>  
> +#define GUC_HOST_INTERRUPT			XE_REG(0x1901f0)
> +
>  #define VF_SW_FLAG(n)				XE_REG(0x190240 + (n) * 4)
>  #define VF_SW_FLAG_COUNT			4
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation