[Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
Matt Roper
matthew.d.roper at intel.com
Mon Sep 18 22:43:44 UTC 2023
On Mon, Sep 18, 2023 at 04:06:58PM -0500, Lucas De Marchi wrote:
> On Fri, Sep 15, 2023 at 12:50:41PM -0700, Matt Roper wrote:
> > On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> > > From: Clint Taylor <clinton.a.taylor at intel.com>
> > >
> > > We use multiple variables for HDMI and DisplayPort to store the value of
> > > DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> > > to just one in struct intel_digital_port. This is a preparation step for
> > > future changes in D2D enable/disable sequence for xe2lpd that need to
> > > save some additional bits.
> > >
> > > Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> > > Cc: Gustavo Sousa <gustavo.sousa at intel.com>
> > > Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> > > Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
> > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > 2 files changed, 18 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 4668de45d6fe..29c9386659ff 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >
> > > /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> > > - intel_dp->DP = dig_port->saved_port_bits |
> > > + dig_port->saved_port_bits |=
> >
> > Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
> > and DDI_A_4_LANES, either based on a value we readout from hardware at
> > startup, or based on VBT settings. So it was a value of some
> > fundamental settings that we "saved" once at startup time and could then
> > just re-use thereafter.
> >
> > If we're going to start saving per-modeset information (such as lane
> > count and link rate), then that's a pretty fundamental change to the
> > purpose of this field, and "saved_port_bits" doesn't really feel like an
> > appropriate name anymore. We should probably rename it and add some
> > documentation on the field explaining exactly what its purpose is and
> > how/when it gets updated.
>
> I will let Clint chime in as the original author here, but from what
> I can see this is basically a saved value of DDI_BUF_CTL(port), to be
> written when appropriate. We have more than just
> DDI_BUF_PORT_REVERSAL and DDI_A_4_LANES.
I think you grepped the wrong tree. The output you pasted is where
saved_port_bits is being used after this LNL series gets applied. The
usage of this field on today's drm-tip is just:
drivers/gpu/drm/i915/display/intel_cx0_phy.c:2706: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_display_types.h:1827: u32 saved_port_bits;
drivers/gpu/drm/i915/display/intel_tc.c:362: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c:333: intel_dp->DP = dig_port->saved_port_bits |
drivers/gpu/drm/i915/display/intel_ddi.c:2259: dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c:2389: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c:3214: buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c:3221: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c:4505: if (dig_port->saved_port_bits & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_ddi.c:4543: dig_port->saved_port_bits |= DDI_A_4_LANES;
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4965: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c-4966- intel_de_read(dev_priv, DDI_BUF_CTL(port))
drivers/gpu/drm/i915/display/intel_ddi.c-4967- & DDI_BUF_PORT_REVERSAL;
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4969: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c-4970- intel_de_read(dev_priv, DDI_BUF_CTL(port))
drivers/gpu/drm/i915/display/intel_ddi.c-4971- & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4974: dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
I.e., using it as a cached copy of DDI_BUF_CTL is a large change from
the existing code; previously it was an unchanging stash of just those
two specific bits from startup-time.
I'm not saying that it's wrong to make that change, just that we're
using it for a completely different purpose from today's drm-tip so I
think we need to document that carefully and make it clear what the
intended new usage is.
Matt
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= signal_levels;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_A_4_LANES)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_A_4_LANES;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_display_types.h: u32 saved_port_bits;
> drivers/gpu/drm/i915/display/intel_dp.c: dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> drivers/gpu/drm/i915/display/intel_tc.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> Lucas De Marchi
>
> >
> > > DDI_PORT_WIDTH(crtc_state->lane_count) |
> > > DDI_BUF_TRANS_SELECT(0);
> > >
> > > if (DISPLAY_VER(i915) >= 14) {
> > > if (intel_dp_is_uhbr(crtc_state))
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> > > else
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> > > }
> > >
> > > if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > > - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > > - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > > }
> > >
> > > @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > int level = intel_ddi_level(encoder, crtc_state, 0);
> > > enum port port = encoder->port;
> > > u32 signal_levels;
> > > @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
> > > signal_levels);
> > >
> > > - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> > > - intel_dp->DP |= signal_levels;
> > > + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> > > + dig_port->saved_port_bits |= signal_levels;
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > }
> > >
> > > @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > struct drm_connector *connector = conn_state->connector;
> > > enum port port = encoder->port;
> > > enum phy phy = intel_port_to_phy(dev_priv, port);
> > > - u32 buf_ctl;
> > >
> > > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > > crtc_state->hdmi_high_tmds_clock_ratio,
> > > @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > * is filled with lane count, already set in the crtc_state.
> > > * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> > > */
> > > - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > if (DISPLAY_VER(dev_priv) >= 14) {
> > > u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> > > u32 port_buf = 0;
> > > @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> > > XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
> > >
> > > - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> > > + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> > > } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> > > drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> > > - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > >
> > > @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > > mtl_port_buf_ctl_program(encoder, crtc_state);
> > >
> > > /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> > > @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > > (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
> > > adlp_tbt_to_dp_alt_switch_wa(encoder);
> > >
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 189c5737e63a..2346cd32f5a7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> > > intel_dp->pps.active_pipe = INVALID_PIPE;
> > >
> > > /* Preserve the current hw state. */
> > > - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> > > + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> >
> > Isn't this going to potentially clobber the lane reversal setting we
> > determined from the VBT near the beginning of intel_ddi_init()?
> >
> >
> > Matt
> >
> > > intel_dp->attached_connector = intel_connector;
> > >
> > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
> > > --
> > > 2.40.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
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