[Intel-xe] [PATCH 2/2] drm/xe/xe2: Report number of Xe2 EUs

[Souza, Jose]

+ Other UMD contacts

On Wed, 2023-09-20 at 14:50 -0700, Matt Roper wrote:
> On Wed, Sep 20, 2023 at 02:21:03PM -0700, Lucas De Marchi wrote:
> > With Xe2, one bit in the fuse enables one Xe2 EU.  Note that although
> > Bspec 62564 still refers to 1 bit == a pair of EUs, this is about the
> > legacy number according to Bspec 70820.
> 
> +Cc Jose.
> 
> Looking at the bspec history it doesn't appear there's any true hardware
> change here; this is just a terminology change that someone thought
> would make the bspec more clear (so they added "legacy" to the true
> hardware count to distinguish it from the fuse register, and then later
> came back and added a separate "Num EU" column that matches fuse
> register).  And it seems that this attempted terminology change wasn't
> even handled consistently across various platforms.  The equivalent
> bspec pages for most other platforms are still giving only the "legacy"
> numbers, either with or without the "legacy" label in the text.
> 
> But regardless of which terminology is actually more/less confusing on
> that bspec page, what really matters is what our userspace partners
> want.  If we want to change the uapi from reporting the true hardware
> value to reporting the fusing number, we should coordinate that
> behavioral change with them.  And if they're trying to access
> hardware-level ("legacy") EUs independently anywhere and can't just
> operate on pairs, then such a change may not be possible.

In my opinion we should at least start Xe KMD consistent, have all platforms with legacy or actual hardware EU count.
There is any guidance from marketing on this? Mesa has a tool that user can get device information that includes EU count.

Just to put UMD folks in the same page.
This will change the value of XE_TOPO_EU_PER_DSS for LNL.

This is what we have BSpec diagrams and what Xe KMD will return with this patch:
TGL 16 legacy EUs per DSS, max 96 legacy EUs

DG2 16 legacy EUs per DSS, max 512 legacy EUs
PVC 8 actual EUs per DSS, max per tile 512 actual EUs
MTL 16 legacy EUs per DSS, max 128 legacy EUs
LNL 8 actual EUs per DSS, max 64 actual/128 legacy EUs

Maybe rename XE_TOPO_EU_PER_DSS to the type decided so no one gets it wrong, XE_TOPO_LEGACY_EU_PER_DSS or XE_TOPO_ACTUAL_EU_PER_DSS.

> 
> 
> Matt
> 
> > 
> > Bspec: 70820, 70821, 62564
> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_gt_topology.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> > index 011ad7f2325c..878f3ed7bc26 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> > @@ -49,8 +49,8 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
> >  	if (GRAPHICS_VERx100(xe) < 1250)
> >  		reg_val = ~reg_val & XELP_EU_MASK;
> >  
> > -	/* On PVC, one bit = one EU */
> > -	if (GRAPHICS_VERx100(xe) == 1260) {
> > +	if (GRAPHICS_VERx100(xe) >= 2000 || GRAPHICS_VERx100(xe) == 1260) {
> > +		/* One bit == one EU */
> >  		val = reg_val;
> >  	} else {
> >  		/* All other platforms, one bit = 2 EU */
> > -- 
> > 2.40.1
> > 
>