✗ CI.checkpatch: warning for Enable display support for Battlemage

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage
URL   : https://patchwork.freedesktop.org/series/132430/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
35057f376b5337039b258ae4c66ed9218f4b3fb8
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b5ea86147e19910e0b2bd8e95bf2b27258bcf15c
Author: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
Date:   Mon Apr 15 13:44:23 2024 +0530

    drm/xe/bmg: Enable the display support
    
    Enable the display support for Battlemage
    
    Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
    Reviewed-by: Shekhar Chauhan <shekhar.chauhan at intel.com>
+ /mt/dim checkpatch 1bfe3965a846936d93b6e69385e53f1bd1c3b889 drm-intel
14d17879d769 drm/xe/display: Lane reversal requires writes to both context lanes
506a61b4ffdc drm/i915/display: Enable RM timeout detection
2ac2879d7ea8 drm/i915/bmg: Define IS_BATTLEMAGE macro
-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:545:
+#define IS_LUNARLAKE(i915) (0 && i915)

-:36: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues
#36: FILE: drivers/gpu/drm/i915/i915_drv.h:546:
+#define IS_BATTLEMAGE(i915)  (0 && i915)

total: 0 errors, 0 warnings, 2 checks, 16 lines checked
adef17830194 drm/i915/xe2hpd: Skip CCS modifiers
-:10: WARNING:TYPO_SPELLING: 'auxillary' may be misspelled - perhaps 'auxiliary'?
#10: 
auxillary surface in the plane, containing the CCS data.  But on
^^^^^^^^^

-:12: WARNING:TYPO_SPELLING: 'auxillary' may be misspelled - perhaps 'auxiliary'?
#12: 
part of the plane. It contains no auxillary surface.
                                  ^^^^^^^^^

-:41: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#41: FILE: drivers/gpu/drm/i915/display/intel_fb.c:435:
+	if (intel_fb_is_ccs_modifier(md->modifier)) {
+

total: 0 errors, 2 warnings, 1 checks, 22 lines checked
f8f4358f049e drm/i915/xe2hpd: Initial cdclk table
c69218a7f004 drm/i915/bmg: Extend DG2 tc check to future
e3948fff940a drm/i915/xe2hpd: Properly disable power in port A
e9b4295e8104 drm/i915/xe2hpd: Add new C20 PHY SRAM address
-:78: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2201:
+									  PHY_C20_B_MPLLB_CNTX_CFG(i915, i));

-:84: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2205:
+									  PHY_C20_A_MPLLB_CNTX_CFG(i915, i));

-:94: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2213:
+									  PHY_C20_B_MPLLA_CNTX_CFG(i915, i));

-:100: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#100: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2217:
+									  PHY_C20_A_MPLLA_CNTX_CFG(i915, i));

total: 0 errors, 4 warnings, 0 checks, 203 lines checked
5664d016efc4 drm/i915/xe2hpd: Add support for eDP PLL configuration
98be3aae9986 drm/i915/xe2hpd: update pll values in sync with Bspec
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matt Roper <matthew.d.roper at intel.com'
#13: 
Reviewed-by: Matt Roper <matthew.d.roper at intel.com

total: 1 errors, 0 warnings, 0 checks, 63 lines checked
9151aefab8e2 drm/i915/xe2hpd: Add display info
b5cade99f771 drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes
2b801333a2fd drm/i915/xe2hpd: Add max memory bandwidth algorithm
6ea6381ad033 drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
f00f633a5ed2 drm/i915/bmg: BMG should re-use MTL's south display logic
7f9d538efe70 Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
e01ce30cabb7 drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
f2c893b21c25 drm/xe/gt_print: add xe_gt_err_once()
96b97cb17100 drm/xe/device: implement transient flush
a82acd5c86e9 drm/i915/display: perform transient flush
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#58: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 76 lines checked
b5ea86147e19 drm/xe/bmg: Enable the display support