[PATCH 3/3] drm/xe/pciids: separate ARL and MTL PCI IDs

[Chauhan, Shekhar]

On 9/5/2024 1:16 PM, Jani Nikula wrote:
> On Thu, 05 Sep 2024, "Chauhan, Shekhar" <shekhar.chauhan at intel.com> wrote:
>> On 9/4/2024 3:16 PM, Jani Nikula wrote:
>>> Avoid including PCI IDs for one platform to the PCI IDs of another. It's
>>> more clear to deal with them completely separately at the PCI ID macro
>>> level.
>>>
>>> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan at intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/xe_pci.c   |  1 +
>>>    include/drm/intel/xe_pciids.h | 13 ++++++++-----
>>>    2 files changed, 9 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>> index b1cf21d77def..5c5eef2ae725 100644
>>> --- a/drivers/gpu/drm/xe/xe_pci.c
>>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>>> @@ -394,6 +394,7 @@ static const struct pci_device_id pciidlist[] = {
>>>    	XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
>>>    	XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
>>>    	XE_PVC_IDS(INTEL_VGA_DEVICE, &pvc_desc),
>>> +	XE_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
>> With this approach of segregating PCI IDs of two platforms, wouldn't it
>> make more sense to have two separate platform descriptors as well, say,
>> mtl_desc and a new one "arl_desc"?
> Not if they are exactly the same.
>
>>>    	XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
>>>    	XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
>>>    	XE_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>>> diff --git a/include/drm/intel/xe_pciids.h b/include/drm/intel/xe_pciids.h
>>> index 334ab02ed6ca..67baa7c2246a 100644
>>> --- a/include/drm/intel/xe_pciids.h
>>> +++ b/include/drm/intel/xe_pciids.h
>>> @@ -176,16 +176,19 @@
>>>    	XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
>>>    	XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
>>>    
>>> -/* MTL / ARL */
>>> +/* ARL */
>>> +#define XE_ARL_IDS(MACRO__, ...)		\
>>> +	MACRO__(0x7D41, ## __VA_ARGS__),	\
>>> +	MACRO__(0x7D51, ## __VA_ARGS__),        \
>>> +	MACRO__(0x7D67, ## __VA_ARGS__),	\
>>> +	MACRO__(0x7DD1, ## __VA_ARGS__)
>>> +
>> Also, if we're following platform public release timelines, can we have
>> MTL block of PCI IDs above the ARL block?
> Can do if it matters.
No big deal if it doesn't matter much.
>
> BR,
> Jani.
>
>>> +/* MTL */
>>>    #define XE_MTL_IDS(MACRO__, ...)		\
>>>    	MACRO__(0x7D40, ## __VA_ARGS__),	\
>>> -	MACRO__(0x7D41, ## __VA_ARGS__),	\
>>>    	MACRO__(0x7D45, ## __VA_ARGS__),	\
>>> -	MACRO__(0x7D51, ## __VA_ARGS__),        \
>>>    	MACRO__(0x7D55, ## __VA_ARGS__),	\
>>>    	MACRO__(0x7D60, ## __VA_ARGS__),	\
>>> -	MACRO__(0x7D67, ## __VA_ARGS__),	\
>>> -	MACRO__(0x7DD1, ## __VA_ARGS__),        \
>>>    	MACRO__(0x7DD5, ## __VA_ARGS__)
>>>    
>>>    /* PVC */

-- 
-shekhar