[PATCH] drm/xe/oa: Enable Xe2+ PES disaggregation

[Dixit, Ashutosh]

On Tue, 10 Sep 2024 10:04:32 -0700, Lucas De Marchi wrote:
>

Hi Lucas,

We had a whole email thread to figure this out :/

> On Mon, Sep 09, 2024 at 09:59:33AM GMT, Ashutosh Dixit wrote:
> > Xe2+ PES disaggregation for OAG needs to be enabled to obtain disaggregated
> > metrics when disaggregated data is needed. There is no uapi impact of this
>
> it looks like the *control* for disaggregated data is only available on
> xe2

Correct, that is why the check below (also this is available only for OAG,
not say for OAM):

	if (GRAPHICS_VER(stream->oa->xe) >= 20 &&
	    stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG)

> and we always use disaggregated, right?

No we don't, please see below.

>
> > change.
> >
> > v2: Minor change to commit message
> >
> > Bspec: 61101
>
> "Note: After enabling desired disaggregation mode/s using this control
> field, PES MODE_SELECT field is used to configure appropriate
> disaggregation mode of corresponding PEC."
>
> Apparently MODE_SELECT == Aggregated is the hw default for xe2. Don't
> we need to program anything else?

So the code in this patch only enables disaggregation, this additional step
(PES_MODE_SELECT) is still needed to actually use disaggregation. However
this second step is done via OA configurations which come in from userspace
(using add_config observation stream op). So userspace can request either
aggregated or disaggregated data depending on the OA config it programs.

The goal of this patch is only to enable disaggregation so userspace can
use it if they want, otherwise they can't, they can only use
aggregated.

That is why this is a "Fix", since this was missed out previously.

> > Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
> > Cc: stable at vger.kernel.org
>
> If double checking above and this is sufficient, feel free to add my

Thanks, done!

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

> > ---
> > drivers/gpu/drm/xe/regs/xe_oa_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_oa.c           | 4 ++++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_oa_regs.h b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > index 1189f5a540a82..a9b0091cb7ee1 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_oa_regs.h
> > @@ -52,6 +52,7 @@
> > #define  OAG_OABUFFER_MEMORY_SELECT		REG_BIT(0) /* 0: PPGTT, 1: GGTT */
> >
> > #define OAG_OACONTROL				XE_REG(0xdaf4)
> > +#define  OAG_OACONTROL_OA_PES_DISAG_EN		REG_GENMASK(27, 22)
> > #define  OAG_OACONTROL_OA_CCS_SELECT_MASK	REG_GENMASK(18, 16)
> > #define  OAG_OACONTROL_OA_COUNTER_SEL_MASK	REG_GENMASK(4, 2)
> > #define  OAG_OACONTROL_OA_COUNTER_ENABLE	REG_BIT(0)
> > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> > index 63286ed8457fa..0369cc016f6ab 100644
> > --- a/drivers/gpu/drm/xe/xe_oa.c
> > +++ b/drivers/gpu/drm/xe/xe_oa.c
> > @@ -440,6 +440,10 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
> >	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
> >		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
> >
> > +	if (GRAPHICS_VER(stream->oa->xe) >= 20 &&
> > +	    stream->hwe->oa_unit->type == DRM_XE_OA_UNIT_TYPE_OAG)
> > +		val |= OAG_OACONTROL_OA_PES_DISAG_EN;
> > +
> >	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
> > }
> >
> > --
> > 2.41.0
> >