[PATCH v3 1/5] drm/xe/bo: fix alignment with non-4KiB kernel page sizes
Matthew Brost
matthew.brost at intel.com
Fri Aug 8 21:55:50 UTC 2025
On Sat, Aug 09, 2025 at 06:11:58AM +0900, Simon Richter wrote:
> Hi,
>
> On 7/28/25 22:30, Rodrigo Vivi wrote:
>
> > > - drm_gem_private_object_init(&xe->drm, &bo->ttm.base, size);
> > > + drm_gem_private_object_init(&xe->drm, &bo->ttm.base, aligned_size);
>
> > but this is strange.
> > think that we could get rid of the aligned_size variable and only go with
> > size = ALIGN(size, PAGE_SIZE)
>
> I'm going through this code, and it is more horrible than anticipated.
>
> The problematic path that makes smaller allocations comes from xe_pt_create,
> where a 4k BO is created for a page table. This needs to be CPU visible as
> well, so in theory it needs to be 16/64/256k aligned, depending on
Ah, no.
Yes, PT BOs need to be CPU-visible for the KMD. However, PT BOs are in
VRAM, and the VRAM mapping is a large one set up at driver load (i.e.,
the VRAM BAR is mapped, and individual VRAM mappings are just offsets
within that mapping).
There are, however, other issues. We discussed this previously here [1].
It seems doable but more complicated than I originally thought. Feel
free to take a pass at it.
[1] https://patchwork.freedesktop.org/patch/639626/?series=145445&rev=2
> PAGE_SIZE. Extending it is wasteful, but that's what we do here.
>
> Using the original size makes the mappings fail, because later it wants to
> map SZ_4K >> PAGE_SHIFT (== 0) pages.
>
> I wonder if there should be a way to merge smaller allocations, maybe even
> special-case page table BOs here (userspace merges smaller allocations
> itself, so it should never request less than PAGE_SIZE).
>
Like implemented a sub-allocator for BOs in the KMD? That seems unlikely
to be accepted.
Matt
> I've talked[1] to the Mesa people, and because they have their own
> allocator, it should be okay to define the DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT
> parameter as "minimum alignment that is okay for any userspace BO type" (as
> opposed to "minimum alignment for VRAM BOs", which would require Mesa to
> also align to sysconf(_SC_PAGESIZE) for CPU visible BOs).
>
> For some reason, everyone tries to avoid setting flags to clarify what they
> want. Mesa does not set the flag for "this BO needs to be CPU visible" if
> there is no VRAM that doesn't fit in the aperture, so the kernel can't
> enforce alignment if the CPU has stricter requirements than the GPU. The
> kernel would ignore the flag anyway, but that's not the point.
>
> Simon
>
> [1] https://gitlab.freedesktop.org/mesa/mesa/-/issues/13658
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