[PATCH v3 2/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset
Poosa, Karthik
karthik.poosa at intel.com
Thu Jun 5 10:00:34 UTC 2025
Can you change patch title to
Add PMT offsets for G-state and PCIe link state residency counters for BMG
On 03-06-2025 23:42, Soham Purkait wrote:
> Add G-State residency and pcie link state residency
> offset macros for G2, G6, G8, G10, ModS and L0, L1, L1.2
> respectively.
Add PMT offsets for G-states (G2, G6, G8, G10, ModS) and
PCIe link states(L0, L1, L1_2) residency counters, for BMG.
>
> Signed-off-by: Soham Purkait <soham.purkait at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_pmt.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
> index b0efd9b48d1e..4e377b6eac92 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
> @@ -21,4 +21,14 @@
> #define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
> #define SG_REMAP_BITS REG_GENMASK(31, 24)
>
> +#define BMG_G2_RESIDENCY_OFFSET (0x530)
> +#define BMG_G6_RESIDENCY_OFFSET (0x538)
> +#define BMG_G8_RESIDENCY_OFFSET (0x540)
> +#define BMG_G10_RESIDENCY_OFFSET (0x548)
> +#define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
> +
> +#define PCIE_LINK_L0_RESIDENCY_COUNTER (0x570)
> +#define PCIE_LINK_L1_RESIDENCY_COUNTER (0x578)
> +#define PCIE_LINK_L1_2_RESIDENCY_COUNTER (0x580)
> +
> #endif
Can you change COUNTER to OFFSET ie. PCIE_LINK_LX_X_RESIDENCY_OFFSET
Also, are these offsets applicable only for BMG ? Based on that you can
keep/remove BMG prefix.
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