[PATCH 8/9] drm/i915/wcl: C10 phy connected to port A and B

[Matt Roper]

On Sat, Jun 07, 2025 at 01:21:03AM +0530, Dnyaneshwar Bhadane wrote:
> WCL added a c10 phy connected to port B. PTL code is currently
> restricting c10 to phy_a only.

This seems like it's a characteristic of the platform rather than the IP
itself.  We should probably go ahead and break WCL out into its own
display platform that we can match against rather than assuming WCL only
uses display 30.02 and vice-versa.  Or maybe we can just update the
existing PTL condition if this function would never be called on PTL
with a non-existent PHY B?


Matt

> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 75caccb65513..59eee0edef79 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -40,6 +40,9 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder);
>  
> +	if ((DISPLAY_VERx100(display) == 3002) && phy < PHY_C)
> +		return true;
> +
>  	if (display->platform.pantherlake && phy == PHY_A)
>  		return true;
>  
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation