[PATCH] drm/xe: Move LRC_ENGINE_ID_PPHWSP_OFFSET outside of parallel offset

[Umesh Nerlige Ramappa]

On Thu, Jun 12, 2025 at 10:28:50AM -0700, Matthew Brost wrote:
>The parallel scratch layout spans 2k and LRC_ENGINE_ID_PPHWSP_OFFSET
>lands within than space. This happens to be ok as the offset lands in
>reserved part of guc_sched_wq_desc, but for future safety move
>LRC_ENGINE_ID_PPHWSP_OFFSET to the unused offset of 1024 below parallel
>scratch layout.

Oh, didn't know that. If you could add that info in a comment above
LRC_PARALLEL_PPHWSP_OFFSET, it would help anyone adding new stuff in
future. Ideally we should update the bspec at some point here - 77575
and guide everyone to look there for overlaps.

Change LGTM from utilization perspective, so with or without the above,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>

Thanks,
Umesh

>
>Signed-off-by: Matthew Brost <matthew.brost at intel.com>
>---
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>index 529c6a972a55..6fb2a2ca4e78 100644
>--- a/drivers/gpu/drm/xe/xe_lrc.c
>+++ b/drivers/gpu/drm/xe/xe_lrc.c
>@@ -654,8 +654,8 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> #define LRC_SEQNO_PPHWSP_OFFSET 512
> #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
>+#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> #define LRC_PARALLEL_PPHWSP_OFFSET 2048
>-#define LRC_ENGINE_ID_PPHWSP_OFFSET 2096
>
> u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> {
>-- 
>2.34.1
>