[PATCH] drm/xe: Move LRC_ENGINE_ID_PPHWSP_OFFSET outside of parallel offset
Matthew Brost
matthew.brost at intel.com
Fri Jun 13 20:12:23 UTC 2025
On Fri, Jun 13, 2025 at 09:38:12AM -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Jun 12, 2025 at 10:28:50AM -0700, Matthew Brost wrote:
> > The parallel scratch layout spans 2k and LRC_ENGINE_ID_PPHWSP_OFFSET
> > lands within than space. This happens to be ok as the offset lands in
> > reserved part of guc_sched_wq_desc, but for future safety move
> > LRC_ENGINE_ID_PPHWSP_OFFSET to the unused offset of 1024 below parallel
> > scratch layout.
>
> Oh, didn't know that. If you could add that info in a comment above
I'll add a comment when merging this.
> LRC_PARALLEL_PPHWSP_OFFSET, it would help anyone adding new stuff in
> future. Ideally we should update the bspec at some point here - 77575
> and guide everyone to look there for overlaps.
>
Yea, that would be good to make sure we are not clobbering anything the
GuC / HW is using in our software defined state here.
Ideally I want kernel doc describing the entire layout of LRC BO too as
I continually forget how it is laid out and have reseverse engine the
code.
Matt
> Change LGTM from utilization perspective, so with or without the above,
>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
>
> Thanks,
> Umesh
>
> >
> > Signed-off-by: Matthew Brost <matthew.brost at intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> > index 529c6a972a55..6fb2a2ca4e78 100644
> > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > @@ -654,8 +654,8 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
> > #define LRC_SEQNO_PPHWSP_OFFSET 512
> > #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
> > #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
> > +#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
> > #define LRC_PARALLEL_PPHWSP_OFFSET 2048
> > -#define LRC_ENGINE_ID_PPHWSP_OFFSET 2096
> >
> > u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
> > {
> > --
> > 2.34.1
> >
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