[PATCH 2/2] drm/xe: Copy cpu_caching when importing DMA-BUF.

[Maarten Lankhorst]

Hey,

On 2025-03-21 11:23, Thomas Hellström wrote:
> Hi, Maarten.
> 
> On Thu, 2025-03-20 at 22:15 +0100, Maarten Lankhorst wrote:
>> When testing xe with P2PDMA DMA-BUF import,
>> VM_BIND was failing because cpu_caching was not set.
>>
>> Set cpu_caching if available from another xe driver,
>> to allow uncached VM_BIND on imported DMA-BUF.
>>
>> Signed-off-by: Maarten Lankhorst <dev at lankhorst.se>
> 
> I don't think this is correct, we shouldn't assume anything about
> imported dma-bufs, really. If we do we might end up in a situation
> where code works for dma-bufs imported from one device but not from
> another.
> 
> I think what we can do is to relax the COH mode check. It only really
> matters on IGPU. On DGPU, all accesses to system memory is coherent.
> 
> Next step would perhaps be to assume that on p2p access, a dma-buf is
> coherently cleared when all KERNEL dma-fences are signaled, but that
> would require a cross-driver agreement, so in essence allow non-
> coherent VM_BIND to device memory. This would matter only for IGPU
> mapping a device p2p.
> 
> /Thomas

So would something like this work instead?

----8<----
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index fed4b97d1882d..fb15de880ae21 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -2990,12 +2990,14 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
 				 bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) {
 			return -EINVAL;
 		}
-	} else if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE)) {
+	} else if (XE_IOCTL_DBG(xe, !IS_DGFX(xe) && coh_mode == XE_COH_NONE)) {
 		/*
 		 * Imported dma-buf from a different device should
 		 * require 1way or 2way coherency since we don't know
 		 * how it was mapped on the CPU. Just assume is it
 		 * potentially cached on CPU side.
+		 *
+		 * On a discrete GPU, all access to system memory is coherent.
 		 */
 		return -EINVAL;
 	}