✗ CI.checkpatch: warning for Panel Replay + Adaptive sync

[Patchwork]

== Series Details ==

Series: Panel Replay + Adaptive sync
URL   : https://patchwork.freedesktop.org/series/148540/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1777fd7717cbf2f3d7dcf1830d75be79cfd596c8
Author: Jouni Högander <jouni.hogander at intel.com>
Date:   Fri May 2 11:59:02 2025 +0300

    drm/i915/psr: Do not disable Panel Replay in case VRR is enabled
    
    This patch is allowing Panel Replay with VRR. All VRR modes are supposed to
    work with Panel Replay.
    
    Bspec: 68920, 68925
    Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
+ /mt/dim checkpatch b99e82e12d60e6c2e158f8c810a11740c07f2196 drm-intel
eb27d7c6974c drm/dp: Add Panel Replay capability bits from DP2.1 specification
5f9c5f57b9f5 drm/i915/psr: Read both Panel Replay capability registers from DPCD
c44efca90668 drm/i915/alpm: Add PR_ALPM_CTL register definitions
-:28: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:275:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2	REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0)

-:29: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:276:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1)

-:30: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:277:
+#define  PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2		REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2)

total: 0 errors, 3 warnings, 0 checks, 16 lines checked
e217eb413b77 drm/i915/alpm: Write PR_ALPM_CTL register
-:26: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:354:
+			if (intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)

-:28: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:356:
+			if (!(intel_dp->pr_dpcd[1] & DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

total: 0 errors, 2 warnings, 0 checks, 18 lines checked
5764ffcc4e4c drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR
7606d8c8416b drm/i915/alpm: Add new interface to check if AUXLess ALPM is used
88715491e18d drm/i915/alpm: Move port alpm configuration
-:74: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#74: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:418:
+			PORT_ALPM_CTL_SILENCE_PERIOD(

-:77: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#77: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:421:
+			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(

-:79: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#79: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:423:
+			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(

-:81: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#81: FILE: drivers/gpu/drm/i915/display/intel_alpm.c:425:
+			PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(

total: 0 errors, 0 warnings, 4 checks, 98 lines checked
053b12d23b8d drm/i915/display: Add PHY_CMN1_CONTROL register definitions
58ad55f75c14 drm/i915/display: Add function to configure LFPS sending
7036f7a6e107 drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP
-:24: WARNING:LONG_LINE: line length of 139 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:338:
+#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)

-:27: WARNING:LONG_LINE: line length of 138 exceeds 100 columns
#27: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:340:
+#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)

total: 0 errors, 2 warnings, 0 checks, 10 lines checked
1777fd7717cb drm/i915/psr: Do not disable Panel Replay in case VRR is enabled