[PATCH v4 0/5] drm/xe/hwmon: Add mailbox power limits, PL2, read energy from PMT
Karthik Poosa
karthik.poosa at intel.com
Tue May 6 15:30:53 UTC 2025
Add support manage power limits through pcode mailboxes.
Enable PL2 support through powerX_cap.
Expose PL2 interval through powerX_cap_interval.
Read energy status from PMT instead of MMIO.
Move power2_crit to power1_crit.
v2:
- Addressed review comments from Badal.
- Clamp the power limits maximum to BIOS default value due to
HSD:16027383332.
RFC patch: https://patchwork.freedesktop.org/series/148148/
Karthik Poosa (5):
drm/xe/hwmon: Add support to manage power limits though mailbox
drm/xe/hwmon: Move card reactive critical power under channel card
drm/xe/hwmon: Add support to manage PL2 though mailbox
drm/xe/hwmon: Expose powerX_cap_interval
drm/xe/hwmon: Read energy status from PMT
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 64 ++-
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 10 +-
drivers/gpu/drm/xe/regs/xe_pcode_regs.h | 9 +-
drivers/gpu/drm/xe/regs/xe_pmt.h | 2 +
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_hwmon.c | 475 +++++++++++++-----
drivers/gpu/drm/xe/xe_pci.c | 5 +
drivers/gpu/drm/xe/xe_pcode.c | 11 +
drivers/gpu/drm/xe/xe_pcode.h | 3 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 +
drivers/gpu/drm/xe/xe_vsec.c | 4 +-
drivers/gpu/drm/xe/xe_vsec.h | 4 +
12 files changed, 465 insertions(+), 133 deletions(-)
--
2.25.1
More information about the Intel-xe
mailing list