[PATCH v2] drm/xe/xe2hpg: Add Wa_22021007897

[Matt Roper]

On Thu, May 08, 2025 at 06:55:52AM -0700, Upadhyay, Tejas wrote:
> 
> 
> > -----Original Message-----
> > From: Bhatia, Aradhya <aradhya.bhatia at intel.com>
> > Sent: 07 May 2025 15:41
> > To: Roper, Matthew D <matthew.d.roper at intel.com>
> > Cc: Intel XE List <intel-xe at lists.freedesktop.org>; Upadhyay, Tejas
> > <tejas.upadhyay at intel.com>; Ghimiray, Himal Prasad
> > <himal.prasad.ghimiray at intel.com>; Bhatia, Aradhya
> > <aradhya.bhatia at intel.com>
> > Subject: [PATCH v2] drm/xe/xe2hpg: Add Wa_22021007897
> > 
> > Add Wa_22021007897 for the Xe2_HPG (graphics version: 20.01) platform.
> > It is a permanent workaround, and applicable on all the steppings.
> > 
> > Signed-off-by: Aradhya Bhatia <aradhya.bhatia at intel.com>
> > ---
> > Changes in v2:
> >   - Fix typo in the SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE macro.
> > 
> >  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
> >  drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > index cbb9f7cbcfc0..5cd5ab8529c5 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > @@ -156,6 +156,7 @@
> >  #define XEHPG_SC_INSTDONE_EXTRA2
> > 	XE_REG_MCR(0x7108)
> > 
> >  #define COMMON_SLICE_CHICKEN4			XE_REG(0x7300,
> > XE_REG_OPTION_MASKED)
> > +#define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE	REG_BIT(12)
> >  #define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
> > 
> >  #define COMMON_SLICE_CHICKEN3
> > 	XE_REG(0x7304, XE_REG_OPTION_MASKED)
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> > 6f6563cc7430..67196baa4249 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -827,6 +827,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> > ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1,
> > DIS_CLIP_NEGATIVE_BOUNDING_BOX))
> >  	},
> > +	{ XE_RTP_NAME("22021007897"),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION(2001),
> > ENGINE_CLASS(RENDER)),
> > +	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4,
> > SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
> > +	},
> 
> Changes are ok, but why its LRC WA?

According to bspec 65182, this register (0x7300) is part of the RCS LRC,
so this looks correct.  Note that you need to search for the offset
rather than the name when looking at that page since for some reason
they wrote out the name of this register in long form as "Chicken bit
for Common Slice Register4" rather than using a symbolic name like most
of the other registers.


Matt

> 
> Tejas
> > 
> >  	/* Xe3_LPG */
> >  	{ XE_RTP_NAME("14021490052"),
> > 
> > base-commit: a127cd437da1f18b6ecc9e03226d8e2b2aa79dab
> > --
> > 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation