✓ CI.checkpatch: success for drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed (rev2)
URL   : https://patchwork.freedesktop.org/series/148781/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0dac7c3c17311055a3c036ba7a86e7a6db976b3d
Author: Gareth Yu <gareth.yu at intel.com>
Date:   Fri May 9 17:25:39 2025 +0800

    drm/i915/display: Enforce pipeline flush with DSI HS transfer
    
    With all of the boundary conditions when streaming the commands B2B in our
    validation (part of the reason we added the flush),  the Flush effectively
    serializes the transmission of each command enqueued within the command
    dispatcher to one per V. Blank line which simplifies the behavior of the
    High Speed Arbitration.
    
    So, unless we absolutely have to burst these to the Sink, we should be
    using the Pipeline Flush bit to serialize the commands.
    
    BSPEC: 19742
    
    Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14247
    
    Cc: Suraj Kandpal <suraj.kandpal at intel.com>
    Cc: Jani Nikula <jani.nikula at intel.com>
    Signed-off-by: Gareth Yu <gareth.yu at intel.com>
+ /mt/dim checkpatch 9b56d987e5e378140bae399659d58f3940bb0953 drm-intel
0dac7c3c1731 drm/i915/display: Enforce pipeline flush with DSI HS transfer