[PATCH] drm/i915/display: Enforce pipeline flush with DSI HS transfer

Jani Nikula jani.nikula at intel.com
Fri May 9 09:51:32 UTC 2025


On Fri, 09 May 2025, <gareth.yu at intel.com> wrote:
> From: Gareth Yu <gareth.yu at intel.com>
>
> With all of the boundary conditions when streaming the commands B2B in our
> validation (part of the reason we added the flush),  the Flush effectively
> serializes the transmission of each command enqueued within the command
> dispatcher to one per V. Blank line which simplifies the behavior of the
> High Speed Arbitration.
>
> So, unless we absolutely have to burst these to the Sink, we should be
> using the Pipeline Flush bit to serialize the commands.
>
> BSPEC: 19742
>

No blank lines between trailer lines please.

Spelling: Bspec: ...

> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14247
>

No blank lines between trailer lines please.

The patch subject should indicate versions, i.e. [PATCH v2].

The commit message should have a changelog indicating changes since v1.

Please be considerate towards the reviewers. I don't want to have to
compare the patches to figure out what changed and why.

If it's only the commit message that changed, then no, you are not
supposed to post another version with just commit message changes unless
asked or before you already have Reviewed-by.

BR,
Jani.


> Cc: Suraj Kandpal <suraj.kandpal at intel.com> Cc: Jani Nikula
> <jani.nikula at intel.com> Signed-off-by: Gareth Yu <gareth.yu at intel.com>
> --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
> drivers/gpu/drm/i915/display/icl_dsi_regs.h | 1 + 2 files changed, 3
> insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 402b7b2e1829..f91f27067768 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -191,12 +191,12 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
>  	else
>  		tmp &= ~PAYLOAD_PRESENT;
>  
> -	tmp &= ~VBLANK_FENCE;
> +	tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH);
>  
>  	if (enable_lpdt)
>  		tmp |= LP_DATA_TRANSFER;
>  	else
> -		tmp &= ~LP_DATA_TRANSFER;
> +		tmp |= PIPELINE_FLUSH;
>  
>  	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
>  	tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
> index d4845ac65acc..b601b7632339 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h
> +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
> @@ -272,6 +272,7 @@
>  #define  PAYLOAD_PRESENT		(1 << 31)
>  #define  LP_DATA_TRANSFER		(1 << 30)
>  #define  VBLANK_FENCE			(1 << 29)
> +#define  PIPELINE_FLUSH			(1 << 28)
>  #define  PARAM_WC_MASK			(0xffff << 8)
>  #define  PARAM_WC_LOWER_SHIFT		8
>  #define  PARAM_WC_UPPER_SHIFT		16

-- 
Jani Nikula, Intel


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