[PATCH v5 17/17] drm/i915/vrr: Enable DC Balance bit
Mitul Golani
mitulkumar.ajitkumar.golani at intel.com
Tue May 13 05:17:00 UTC 2025
Enable DC Balance from vrr compute config and also add
enable/disable frame counters for DC Balance odd and even
frame count calculation.
--v2:
Update commit message
--v3:
- Driver should not control adjustment enable bit, as that
is already being controlled by firmware. Release bit from
driver computation.
- Commit message update.
--v4:
- Configure PIPEDMC_EVT_CTL enable/disable call.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5ca71df79430..25e8c76990d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -277,6 +277,9 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+ if (intel_vrr_dc_balance_possible(crtc_state))
+ crtc_state->vrr.dc_balance.enable = true;
}
/*
@@ -663,6 +666,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
if (crtc_state->vrr.dc_balance.enable) {
intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder),
+ ADAPTIVE_SYNC_COUNTER_EN);
intel_pipedmc_dcb_enable(NULL, crtc);
}
}
@@ -680,6 +685,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (old_crtc_state->vrr.dc_balance.enable) {
intel_pipedmc_dcb_disable(NULL, crtc);
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
}
--
2.48.1
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